參數(shù)資料
型號: CY7C63221A-PC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: enCoRe USB Low-speed USB Peripheral Controller
中文描述: 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDIP16
封裝: 0.300 INCH, PLASTIC, DIP-16
文件頁數(shù): 28/49頁
文件大?。?/td> 960K
代理商: CY7C63221A-PC
FOR
FOR
enCoRe
USB
CY7C63221/31A
Document #: 38-08028 Rev. *A
Page 28 of 49
16.0
PS/2 Operation
The CY7C632XX parts are optimized for combination USB or PS/2 devices, through the following features:
1. USB D+ and D
lines can also be used for PS/2 SCLK and SDATA pins, respectively. With USB disabled, these lines can be
placed in a high-impedance state that will pull up to V
CC
. (Disable USB by clearing the Address Enable bit of the USB Device
Address Register,
Figure 14-1
.)
2. An interrupt is provided to indicate a long LOW state on the SDATA pin. This eliminates the need to poll this pin to check for
PS/2 activity. Refer to Section 19.3 for more details.
3. Internal PS/2 pull-up resistors can be enabled on the SCLK and SDATA lines, so no GPIO pins are required for this task (bit
7, USB Status and Control Register,
Figure 13-1
).
4. The controlled slew rate outputs from these pins apply to both USB and PS/2 modes to minimize EMI.
5. The state of the SCLK and SDATA pins can be read, and can be individually driven LOW in an open drain mode. The pins are
read at bits [5:4] of Port 2, and are driven with the Control Bits [2:0] of the USB Status and Control Register.
6. The VREG pin can be placed into a high-impedance state, so that a USB pull-up resistor on the D
/SDATA pin will not interfere
with PS/2 operation (bit 6, USB Status and Control Register).
The PS/2 on-chip support circuitry is illustrated in
Figure 16-1
.
17.0
12-bit Free-running Timer
The 12-bit timer operates with a 1-
μ
s tick, provides two interrupts (128
μ
s and 1.024ms) and allows the firmware to directly time
events that are up to 4 ms in duration. The lower 8 bits of the timer can be read directly by the firmware. Reading the lower 8 bits
latches the upper 4 bits into a temporary register. When the firmware reads the upper 4 bits of the timer, it is actually reading the
count stored in the temporary register. The effect of this is to ensure a stable 12-bit timer value can be read, even when the two
reads are separated in time.
Figure 16-1. Diagram of USB - PS/2 System Connections
D
/SDATA
D+/SCLK
5 k
3.3V
Regulator
5 k
V
CC
USB - PS/2
Driver
1.3 k
VREG
VREG Enable
PS/2 Pull-up
Enable
Port 2.0
On-chip
Off-chip
Port 2.5
Port 2.4
200
相關(guān)PDF資料
PDF描述
CY7C63221A-XC TV 32C 32#20 SKT RECP
CY7C63231A enCoRe USB Low-speed USB Peripheral Controller(enCoRe USB 低速USB外設(shè)控制器)
CY7C64013C Full-Speed USB (12-Mbps)(全速USB(12-Mbps))
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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