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參數(shù)資料
| 型號： | CY7C470-40DMB |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 8K x 9 FIFO, 16K x 9 FIFO 32K x 9 FIFO with Programmable Flags |
| 中文描述： | 8K X 9 OTHER FIFO, 40 ns, CDIP28 |
| 封裝： | 0.600 INCH, SIDE BRAZED, CERDIP-28 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 270K |
| 代理商： | CY7C470-40DMB |
CY7C470
CY7C472
CY7C474
9
Architecture
The CY7C470, CY7C472, and CY7C474 FIFOs consist of an
array of 8,192, 16,384, and 32,768 words of 9 bits each, re-
spectively. The control consists of a read pointer, a write point-
er, a retransmit pointer, control signals (i.e., write, read, mark,
retransmit, and master reset), and flags (i.e., Empty/Full, Half
Full, and Programmable Almost Full/Empty).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the empty condition signi-
fied by the Empty flag (E/F) and Almost Full/Empty flag (PAFE) being
LOW, and Half Full flag (HF) being HIGH. The read pointer, write
pointer, and retransmit pointer are reset to zero. For a valid reset,
Read (R) and Write (W) must be HIGH t
RPW
/t
WPW
before the falling
edge and t
RMR
after the rising edge of MR.
Writing Data to the FIFO
Data can be written to the FIFO when it is not FULL
[11]
. A falling
edge of W initiates a write cycle. Data appearing at the inputs (D
0
–D
8
)
t
SD
before and t
HD
after the rising edge of W will be stored sequen-
tially in the FIFO.
Reading Data from the FIFO
Data can be read from the FIFO when it is not empty
[12]
. A
falling edge of R initiates a read cycle. Data outputs (Q
0
–Q
8
) are in a
high-impedance condition when the FIFO is empty and between read
operations (R HIGH). The falling edge of R during the last read cycle
before the empty condition triggers a high-to-low transition of E/F, pro-
hibiting any further read operations until t
RFF
after a valid write.
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and resent if necessary. Retransmission can start
from anywhere in the FIFO and be repeated without limitation.
The retransmit methodology is as follows: mark the current
value of the read pointer, after an error in subsequent read
operations return to that location and resume reading. This
effectively resends all of the data from the mark point. When
MARK is LOW, the current value of the read pointer is stored. This
operation marks the beginning of the packet to be resent. When RT
is LOW, the read pointer is updated with the mark location. During
each subsequent read cycle, data is read and the read pointer incre-
mented.
Care must be taken when using the retransmit feature. Use the
mark function such that the write pointer does not pass the
mark pointer, because further write operations will overwrite
data.
Programmable Almost Full/Empty Flag
The CY7C470/2/4 offer a variable offset for the Almost Empty
and the Almost Full condition. The offset is loaded into the
programmable flag register (PFR) during a master reset cycle.
While MR is LOW, the PFR can be loaded from Q
8
–Q
0
by pulsing
R LOW or from D
8
–D
0
by pulsing W LOW. The offset options are
listed in Table 2 See Table 1for a description of the six FIFO states.
If the PFR is not loaded during master reset (R and W HIGH) the
default offset will be 256 words from Full and Empty.
Switching Waveforms
(Continued)
R
Full Flag and Write Data Flow-Through Mode
E/F
DATA OUT
W
t
A
t
SD
DATA IN
t
HD
t
WAF
t
PW
t
EFD
t
EFD
7C470–18
DATA VALID
DATA VALID
Notes:
11.
When the FIFO is less than half full, the flags make a LOW-to-HIGH transition on the rising edge of W and make the HIGH-to-LOW transition on the falling edge
of R. If the FIFO is more than half full, the flags make the LOW-to-HIGH transition on the rising edge of R and HIGH-to-LOW transition on the falling edge of W.
12. Full and empty states can be decoded from the Half-Full (HF) and Empty/Full (E/F) flags.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C470-40JC | 8K x 9 FIFO, 16K x 9 FIFO 32K x 9 FIFO with Programmable Flags |
| CY7C470-40JI | 8K x 9 FIFO, 16K x 9 FIFO 32K x 9 FIFO with Programmable Flags |
| CY7C472-25LMB | 8K x 9 FIFO, 16K x 9 FIFO 32K x 9 FIFO with Programmable Flags |
| CY7C474-25LMB | 8K x 9 FIFO, 16K x 9 FIFO 32K x 9 FIFO with Programmable Flags |
| CY7C474-20DMB | 8K x 9 FIFO, 16K x 9 FIFO 32K x 9 FIFO with Programmable Flags |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C470-40JI | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C472-15JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C472-15JI | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C4801-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO, 2 x 256 x 9, Synchronous, 64 Pin, Plastic, QFP |
| CY7C4821-25AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 1K x 9 x 2 64-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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