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參數(shù)資料
| 型號(hào)： | CY7C4425V-15ASC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | OSC 5V SMT 7X5 CMOS PROGRM |
| 中文描述： | 64 X 18 OTHER FIFO, 11 ns, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, STQFP-64 |
| 文件頁(yè)數(shù)： | 13/25頁(yè) |
| 文件大?。?/td> | 409K |
| 代理商： | CY7C4425V-15ASC |
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CY7C4425/4205/4215
CY7C4225/4235/4245
13
Notes:
32. Read from Last Physical Location.
33. Clocks are free running in this case.
34. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t
RTR
.
35. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t
RTR
to update these flags.
Switching Waveforms
(continued)
Read Expansion Out Timing
REN
WCLK
RXO
t
CLKH
t
ENS
Note
t
XO
t
XO
42X5–20
32
Write Expansion InTiming
WCLK
WXI
t
XI
t
XIS
42X5–21
Read Expansion In Timing
RCLK
RXI
t
XI
t
XIS
42X5–22
Retransmit Timing
REN/WEN
FL/RT
t
PRT
t
RTR
42X5–23
EF/FF
and all
async flags
HF/PAE/PAF
[33, 34, 35]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C4245V-15ASC | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4225-10AC | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4225-10AI | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4225-10ASC | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4225-10ASI | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C443-12JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 2K x 9 32-Pin PLCC |
| CY7C443-14DC | 制造商:Cypress Semiconductor 功能描述:FIFO, 2K x 9, Synchronous, 28 Pin, Ceramic, DIP |
| CY7C443-14JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 2K x 9 32-Pin PLCC |
| CY7C443-14JCT | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 2K x 9 32-Pin PLCC T/R |
| CY7C443-30JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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