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參數(shù)資料
| 型號(hào)： | CY7C43686AV-15AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | FIFO |
| 英文描述： | 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO |
| 中文描述： | 16K X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-128 |
| 文件頁數(shù)： | 6/40頁 |
| 文件大?。?/td> | 644K |
| 代理商： | CY7C43686AV-15AC |
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CY7C43646AV
CY7C43666AV
CY7C43686AV
Document #: 38-06026 Rev. *C
Page 6 of 40
PRS2
FIFO2 Partial
Reset
I
A LOW on this pin initializes the FIFO2 Read and Write pointers to the first location
of memory and sets the Port A output register to all zeroes
. During Partial Reset,
the currently selected bus size, endian arrangement, programming method (serial or
parallel), and programmable flag settings are all retained.
RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB
to Read data on
Port B.
A LOW strobe on this pin will retransmit data on FIFO1
. This is achieved by bringing
the Read pointer back to location zero. The user will still need to perform Read opera-
tions to retransmit the data. Retransmit function applies to CY Standard mode only.
A LOW strobe on this pin will retransmit data on FIFO2
. This is achieved by bringing
the Read pointer back to location zero. The user will still need to perform Read opera-
tions to retransmit the data. Retransmit function applies to CY Standard mode only.
A HIGH on this pin selects byte bus (9-bit) size on Port B
. A LOW on this pin selects
word (18-bit) bus size. SIZEB works with BE to select the bus size and endian
arrangement for Port B. The level of SIZEB must be static throughout device operation.
A HIGH on this pin selects byte bus (9-bit) size on Port C
. A LOW on this pin selects
word (18-bit) bus size. SIZEC works with BE to select the bus size and endian
arrangement for Port C. The level of SIZEC must be static throughout device operation.
A LOW on this pin selects serial programming of partial flag offsets
. A HIGH on
this pin selects parallel programming or default offsets (8, 16, or 64).
A HIGH selects a Write operation and a LOW selects a Read operation on Port A
for a LOW-to-HIGH transition of CLKA. The A
0
–
35
outputs are in the HIGH impedance
state when W/RA is HIGH.
WENC must be HIGH to enable a LOW-to-HIGH transition of CLKC
to write data on
Port C.
RENB
Port B Read
Enable
FIFO1
Retransmit
I
RT1
I
RT2
FIFO2
Retransmit
I
SIZEB
Bus Size Select
I
SIZEC
Bus Size Select
I
SPM
Serial
Programming
Port A
Write/Read
Select
Port C Write
Enable
I
W/RA
I
WENC
I
Pin Definitions
(continued)
Signal Name
Description
I/O
Function
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43686AV-7AC | 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO |
| CY7C43686AV-10AI | 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO |
| CY7C43686AV-10AC | 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO |
| CY7M194-10DC | x4 SRAM Module |
| CY7M194-12DC | x4 SRAM Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43686AV-7AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Triple Depth/Width Tri-Bus 16K x 36/16K x 18 x 2 128-Pin TQFP |
| CY7C439-40DMB | 制造商:Cypress Semiconductor 功能描述: |
| CY7C441-14JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 512 x 9 32-Pin PLCC |
| CY7C441-30JC | 制造商:Cypress Semiconductor 功能描述:FIFO, 512 x 9, Synchronous, 32 Pin, Plastic, PLCC |
| CY7C441-30JI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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