參數(shù)資料
型號(hào): CY7C43646AV-10AC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO
中文描述: 1K X 36 BI-DIRECTIONAL FIFO, 8 ns, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-128
文件頁(yè)數(shù): 36/40頁(yè)
文件大?。?/td> 644K
代理商: CY7C43646AV-10AC
CY7C43646AV
CY7C43666AV
CY7C43686AV
Document #: 38-06026 Rev. *C
Page 36 of 40
Note:
68. If Port B is configured for word size, data can be written to the Mail1 register using A
(A
18
35
are
Don
t Care
inputs). In this first case, B
will have valid
data. If Port B is configured for byte size, data can be written to the Mail1 Register using A
0
8
(A
9
35
are
Don
t Care
inputs). In this second case, B
0
8
will have
valid data (B
9
17
will be indeterminate).
Switching Waveforms
(continued)
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
DH
t
DS
W1
t
PMF
t
PMF
t
EN
t
MDV
t
PMR
t
ENS
t
ENH
t
DIS
FIFO1 Output
Register
W1 (Remains valid in Mail1 Register after Read)
CLKA
CSA
W/RA
MBA
ENA
A
0
35
CLKB
MBF1
CSB
MBB
RENB
Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes)
[68]
B
0
17
[37]
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