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參數(shù)資料
| 型號： | CY7C4292 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 128K x9 Deep Sync FIFOs w/Retransmit & Depth Expansion(128Kx9位 深同步先進先出（FIFO）/中斷發(fā)送&深度擴展) |
| 中文描述： | 128K的X9熱賣深度同步FIFO的瓦特/重發(fā) |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 284K |
| 代理商： | CY7C4292 |
PRELIMINARY
64K/128K x9 Deep Sync FIFOs w/
Retransmit & Depth Expansion
CY7C4282
CY7C4292
Cypress Semiconductor Corporation
3901 North First Street
San Jose
September 5, 1997 - Revised November 6, 1997
CA 95134
408-943-2600
Features
High-speed, low-power, first-in first-out (FIFO)
memories
64k x 9 (CY7C4282)
128k x 9 (CY7C4292)
0.5 micron CMOS for optimum speed/power
High-speed, Near Zero Latency (True Dual-Ported
Memory Cell), 100-MHz operation (10 ns read/write cy-
cle times)
Low power
—
I
CC
=40 mA
—
I
SB
= 2 mA
Fully asynchronous and simultaneous read and write
operation
Empty, Full, and Programmable Almost Empty and Al-
most Full status flags
TTL compatible
Retransmit function
Output Enable (OE
)
pin
Independent read and write enable pins
Supports free-running 50% duty cycle clock inputs
Width Expansion Capability
Depth Expansion Capability through token-passing
scheme (no external logic required)
64-pin 10x10 STQFP
Functional Description
The CY7C4282/92 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
devices are 9 bits wide. The CY7C4282/92 can be cascaded
to increase FIFO depth. Programmable features include Al-
most Full/Almost Empty flags. These FIFOs provide solutions for
a wide variety of data buffering needs, including high-speed data ac-
quisition, multiprocessor interfaces, video and communications buff-
ering.
These FIFOs have 9-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and a write-enable
pin (WEN).
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (XI), cas-
cade output (XO), and First Load (FL) pins. The XO pin is connected
to the XI pin of the next device, and the XO pin of the last device
should be connected to the XI pin of the first device. The FL pin of the
first device is tied to V
SS
and the FL pin of all the remaining devices
should be tied to V
CC
When WEN is asserted, data is written into the FIFO on the
rising edge of the WCLK signal. While WEN is held active, data
is continually written into the FIFO on each cycle. The output
port is controlled in a similar manner by a free-running read
clock (RCLK) and a read enable pin (REN). In addition, the
CY7C4282/92 have an output enable pin (OE). The read and
write clocks may be tied together for single-clock operation or
the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
achievable.
FF
Logic Block Diagram
4282–1
THREE-STATE
OUTPUT REGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D
0
8
RCLK
Q
0
8
WEN
WCLK
RS
OE
Dual Port
64K x 9
128K x 9
REN
EXPANSION
LOGIC
FL/RT
XI/LD
PAF/XO
EF
PAE
PAF/XO
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|---|---|
| CY7C43643AV-7AC | 3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching |
| CY7C43643AV | 3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching |
| CY7C43643AV-10AC | 3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching |
| CY7C43643AV-15AC | 3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching |
| CY7C43663AV-10AC | 3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C429-20AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C429-20JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 2K x 9 32-Pin PLCC 制造商:Cypress Semiconductor 功能描述:FIFO CMOS 2KX9 SMD 7C429 PLCC28 |
| CY7C429-20JCT | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 2K x 9 32-Pin PLCC T/R |
| CY7C429-20JXC | 功能描述:先進先出 2Kx9 .300" PARALLEL CASCADEABLE 先進先出 COM RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| CY7C429-20JXCT | 功能描述:先進先出 2Kx9 .300" PARALLEL CASCADEABLE 先進先出 COM RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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