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參數(shù)資料
| 型號(hào)： | CY7C4291V-25JC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs |
| 中文描述： | 128K X 9 OTHER FIFO, 15 ns, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 205K |
| 代理商： | CY7C4291V-25JC |
16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Cypress Semiconductor Corporation
Document #: 38-06013 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised August 25, 2003
Features
3.3V operation for low power consumption and easy
integration into low-voltage systems
High-speed, low-power, first-in first-out (FIFO)
memories
16K × 9 (CY7C4261V)
32K × 9 (CY7C4271V)
64K × 9 (CY7C4281V)
128K × 9 (CY7C4291V)
0.35-micron CMOS for optimum speed/power
High-speed 100-MHz operation (10-ns read/write cycle
times)
Low power
—I
CC
= 25 mA
—I
SB
= 4 mA
Fully asynchronous and simultaneous read and write
operation
Empty, Full, and programmable Almost Empty and
Almost Full status flags
Output Enable (OE) pin
Independent read and write enable pins
Supports free-running 50% duty cycle clock inputs
Width- Expansion capability
32-pin PLCC
Pin-compatible density upgrade to CY7C42X1V family
Pin-compatible 3.3V solutions for CY7C4261/71/81/91
Functional Description
The CY7C4261/71/81/91V are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4261/71/81/91V are pin-compatible to the
CY7C42x1V Synchronous FIFO family. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor inter-
faces, and communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1 and WEN2/LD are held active, data is continually
written into the FIFO on each WCLK cycle. The output port is
controlled in a similar manner by a free-running read clock
(RCLK) and two read enable pins (REN1, REN2). In addition,
the CY7C4261/71/81/91V has an output enable pin (OE). The
read (RCLK) and write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock
frequencies up to 100 MHz are achievable. Depth expansion
is possible using one enable input for system control, while the
other enable is controlled by expansion logic to direct the flow
of data.
LogicBlock Diagram
THREE-STATE
OUTPUT REGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D0
8
RCLK
Q0
8
WEN1
WCLK
RS
OE
Dual Port
RAM Array
16K/32K
64x 9
WEN2/LD
REN1 REN2
EF
PAE
PAF
FF
PLCC
Top View
D
1
D
0
PAF
PAE
RCLK
REN2
V
CC
Q
8
Q
7
Q
6
Q
5
D
8
D
7
D
6
D
5
D
4
D
3
GND
REN1
WCLK
WEN2/LD
D
2
5
6
7
8
9
10
11
12
13
OE
4
3
2
1
31 30
32
21
22
23
24
27
26
28
29
25
14 15 16 17 18 19 20
WEN1
RS
F
Q
0
Q
1
Q
2
Q
3
Q
4
E
CY7C4261V
CY7C4271V
CY7C4281V
CY7C4291V
Pin Configuration
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C4261V-15JC | CONNECTOR ACCESSORY |
| CY7C4281V-15JI | 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs |
| CY7C4281V-25JC | 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs |
| CY7C4261V-10JC | Power Resistor; Series:MK; Resistance:50Mohm; Resistance Tolerance:+/- 1 %; Power Rating:0.75W; Voltage Rating:400V; Temperature Coefficient:+/-50 ppm; Mounting Type:Through Hole; Operating Temp. Min:0 C |
| CY7C4271V-10JC | 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C429-20AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C429-20JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 2K x 9 32-Pin PLCC 制造商:Cypress Semiconductor 功能描述:FIFO CMOS 2KX9 SMD 7C429 PLCC28 |
| CY7C429-20JCT | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 2K x 9 32-Pin PLCC T/R |
| CY7C429-20JXC | 功能描述:先進(jìn)先出 2Kx9 .300" PARALLEL CASCADEABLE 先進(jìn)先出 COM RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| CY7C429-20JXCT | 功能描述:先進(jìn)先出 2Kx9 .300" PARALLEL CASCADEABLE 先進(jìn)先出 COM RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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