- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380216 > CY7C4271V-25JC (CYPRESS SEMICONDUCTOR CORP) 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs PDF資料下載
參數(shù)資料
| 型號(hào)： | CY7C4271V-25JC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs |
| 中文描述： | 32K X 9 OTHER FIFO, 15 ns, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁(yè)數(shù)： | 1/16頁(yè) |
| 文件大小： | 223K |
| 代理商： | CY7C4271V-25JC |
當(dāng)前第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)
16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Cypress Semiconductor Corporation
Document #: 38-06013 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised August 25, 2003
Features
3.3V operation for low power consumption and easy
integration into low-voltage systems
High-speed, low-power, first-in first-out (FIFO)
memories
16K × 9 (CY7C4261V)
32K × 9 (CY7C4271V)
64K × 9 (CY7C4281V)
128K × 9 (CY7C4291V)
0.35-micron CMOS for optimum speed/power
High-speed 100-MHz operation (10-ns read/write cycle
times)
Low power
—I
CC
= 25 mA
—I
SB
= 4 mA
Fully asynchronous and simultaneous read and write
operation
Empty, Full, and programmable Almost Empty and
Almost Full status flags
Output Enable (OE) pin
Independent read and write enable pins
Supports free-running 50% duty cycle clock inputs
Width- Expansion capability
32-pin PLCC
Pin-compatible density upgrade to CY7C42X1V family
Pin-compatible 3.3V solutions for CY7C4261/71/81/91
Functional Description
The CY7C4261/71/81/91V are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4261/71/81/91V are pin-compatible to the
CY7C42x1V Synchronous FIFO family. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor inter-
faces, and communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1 and WEN2/LD are held active, data is continually
written into the FIFO on each WCLK cycle. The output port is
controlled in a similar manner by a free-running read clock
(RCLK) and two read enable pins (REN1, REN2). In addition,
the CY7C4261/71/81/91V has an output enable pin (OE). The
read (RCLK) and write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock
frequencies up to 100 MHz are achievable. Depth expansion
is possible using one enable input for system control, while the
other enable is controlled by expansion logic to direct the flow
of data.
LogicBlock Diagram
THREE-STATE
OUTPUT REGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D0
8
RCLK
Q0
8
WEN1
WCLK
RS
OE
Dual Port
RAM Array
16K/32K
64x 9
WEN2/LD
REN1 REN2
EF
PAE
PAF
FF
PLCC
Top View
D
1
D
0
PAF
PAE
RCLK
REN2
V
CC
Q
8
Q
7
Q
6
Q
5
D
8
D
7
D
6
D
5
D
4
D
3
GND
REN1
WCLK
WEN2/LD
D
2
5
6
7
8
9
10
11
12
13
OE
4
3
2
1
31 30
32
21
22
23
24
27
26
28
29
25
14 15 16 17 18 19 20
WEN1
RS
F
Q
0
Q
1
Q
2
Q
3
Q
4
E
CY7C4261V
CY7C4271V
CY7C4281V
CY7C4291V
Pin Configuration
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C4275 | 32K/64Kx18 Deep Sync FIFOs |
| CY7C4275-10ASC | 32K/64Kx18 Deep Sync FIFOs |
| CY7C4275-10ASI | JT 37C 37#22D SKT PLUG |
| CY7C4275-15ASC | 32K/64Kx18 Deep Sync FIFOs |
| CY7C4275-25ASC | 32K/64Kx18 Deep Sync FIFOs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C4275-10ASC | 功能描述:IC DEEP SYN FIFO 32KX18 64LQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| CY7C4275-10ASI | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 18 64-Pin TQFP |
| CY7C4275-15ASC | 功能描述:IC DEEP SYN FIFO 32KX18 64-STQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| CY7C4275-25ASC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C4275V-10ASC | 功能描述:IC DEEP SYN FIFO 32KX18 64LQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。