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參數(shù)資料
| 型號(hào)： | CY7C4255V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8Kx18 Low Voltage Deep Sync FIFOs(8Kx18低壓深同步先進(jìn)先出（FIFO）) |
| 中文描述： | 8Kx18低壓同步FIFO的深度（8Kx18低壓深同步先進(jìn)先出（FIFO）的） |
| 文件頁數(shù)： | 1/20頁 |
| 文件大小： | 281K |
| 代理商： | CY7C4255V |
32K/64Kx18 Low Voltage Deep Sync FIFOs
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Cypress Semiconductor Corporation
Document #: 38-06012 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 26, 2002
408-943-2600
285V
Features
3.3V operation for low power consumption and easy
integration into low-voltage systems
High-speed, low-power, first-in first-out (FIFO)
memories
8K x 18 (CY7C4255V)
16K x 18 (CY7C4265V)
32K x 18 (CY7C4275V)
64K x 18 (CY7C4285V)
0.35 micron CMOS for optimum speed/power
High-speed 100-MHz operation (10-ns read/write cycle
times)
Low power
—
I
CC
= 30 mA
—
I
SB
= 4 mA
Fully asynchronous and simultaneous read and write
operation
Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
Retransmit function
Output Enable (OE
)
pin
Independent read and write enable pins
Supports free-running 50% duty cycle clock inputs
Width Expansion Capability
Depth Expansion Capability
64-pin 10x10 STQFP
Pin-compatible density upgrade to CY7C42X5V-ASC
families
Pin-compatible 3.3V solutions for CY7C4255/65/75/85
Functional Description
The CY7C4255/65/75/85V are high-speed, low-power, first-in
first-out (FIFO) memories with clocked read and write interfac-
es. All are 18 bits wide and are pin/functionally compatible to
the
CY7C42X5V
Synchronous
CY7C4255/65/75/85V can be cascaded to increase FIFO
depth. Programmable features include Almost Full/Almost
Empty flags. These FIFOs provide solutions for a wide variety of
data buffering needs, including high-speed data acquisition, multipro-
cessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and a write enable
pin (WEN).
When WEN is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is continu-
ally written into the FIFO on each cycle. The output port is controlled
in a similar manner by a free-running read clock (RCLK) and a read
enable pin (REN). In addition, the CY7C4255/65/75/85V have an
output enable pin (OE). The read and write clocks may be tied togeth-
er for single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock frequencies
up to 67 MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI,
RXI), cascade output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of the
next device, and the WXO and RXO pins of the last device should be
connected to the WXI and RXI pins of the first device. The FL pin of
the first device is tied to V
SS
and the FL pin of all the remaining devic-
es should be tied to V
CC
.
FIFO
family.
The
Q
0
–
17
4275V
–
1
THREE-STATE
OUTPUTREGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
EXPANSION
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D
0
–
17
REN
RCLK
FF
EF
PAE
PAF
SMODE
WEN
WCLK
RS
FL/RT
WXI
WXO/HF
OE
RXI
RXO
Logic Block Diagram
High
Density
Dual-Port
RAM Array
8Kx9
16Kx9
32Kx9
64Kx9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C4275V | 32Kx18 Low Voltage Deep Sync FIFOs(32Kx18低壓深同步先進(jìn)先出（FIFO）) |
| CY7C4285V | 64Kx18 Low Voltage Deep Sync FIFOs(64Kx18低壓深同步先進(jìn)先出（FIFO）) |
| CY7C4265V | 16Kx18 Low Voltage Deep Sync FIFOs(16Kx18低壓深同步先進(jìn)先出（FIFO）) |
| CY7C4282V | 64Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion(64Kx9 深同步先進(jìn)先出（FIFO）/中斷發(fā)送&深度擴(kuò)展) |
| CY7C4292V | 128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion(128Kx9低壓深同步先進(jìn)先出（FIFO）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C4255V-10ASXC | 功能描述:先進(jìn)先出 8K X18 LOW VOLTAGE DEEP SYNC 先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| CY7C4255V-15ASC | 功能描述:IC FIFO 8KX18 SYNCHRONOUS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| CY7C4255V-15ASI | 功能描述:IC FIFO 8KX18 SYNCHRONOUS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| CY7C4255V-15ASXC | 功能描述:先進(jìn)先出 8K X18 LOW VOLTAGE DEEP SYNC 先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| CY7C4255V-15ASXI | 功能描述:先進(jìn)先出 8K X18 LOW VOLTAGE DEEP SYNC 先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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