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參數(shù)資料
| 型號(hào)： | CY7C4215V-35ASC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | SERIAL DTE CABLE WITH DB9 FEMALE CONNECTOR |
| 中文描述： | 512 X 18 OTHER FIFO, 20 ns, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, STQFP-64 |
| 文件頁(yè)數(shù)： | 3/25頁(yè) |
| 文件大小： | 409K |
| 代理商： | CY7C4215V-35ASC |
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CY7C4425/4205/4215
CY7C4225/4235/4245
3
Selection Guide
7C42X5-10
100
8
10
3
0.5
8
45
50
7C42X5-15
66.7
10
15
4
1
10
45
50
7C42X5-25
40
15
25
6
1
15
45
50
7C42X5-35
28.6
20
35
7
2
20
45
50
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Operating Current (I
CC2
)
(mA) @ freq=20MHz
Commercial
Industrial
CY7C4425
64 x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C4205
256 x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C4215
512 x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C4225
1K x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C4235
2K x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C4245
4K x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
Density
Packages
Pin Definitions
Signal Name
D
0–17
Q
0–17
WEN
Description
Data Inputs
I/O
I
Function
Data inputs for an 18-bit bus
Data Outputs
O
Data outputs for an 18-bit bus
Write Enable
I
Enables the WCLK input
REN
Read Enable
I
Enables the RCLK input
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-off-
set register.
WXO/HF
Write Expansion
Out/Half Full Flag
O
Dual-Mode Pin:
Single device or width expansion - Half Full status flag.
Cascaded - Write Expansion Out signal, connected to WXI of next device.
EF
Empty Flag
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
value programmed into the FIFO. PAE is asynchronous when V
CC
/SMODE is tied
to V
CC
; it is synchronized to RCLK when V
CC
/SMODE is tied to V
SS
.
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when V
CC
/SMODE is tied to
V
CC
; it is synchronized to WCLK when V
CC
/SMODE is tied to V
SS
.
When LD is LOW, D
0 - 17
(O
0 - 17
) are written (read) into (from) the programma-
ble-flag-offset register.
PAF
Programmable
Almost Full
O
LD
Load
I
FL/RT
First Load/
Retransmit
I
Dual-Mode Pin:
Cascaded - The first device in the daisy chain will have FL tied to V
SS
; all other
devices will have FL tied to V
CC
. In standard mode of width expansion, FL is tied
to V
SS
on all devices.
Not Cascaded - Tied to V
SS
. Retransmit function is also available in standalone
mode by strobing RT.
WXI
Write Expansion
Input
I
Cascaded - Connected to WXO of previous device.
Not Cascaded - Tied to V
SS
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C4205-10AC | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4205-10AI | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4205-10ASC | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4205-10ASI | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4205-10JC | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C421-65AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C421-65JC | 制造商:Cypress Semiconductor 功能描述:512 X 9 OTHER FIFO, 65 ns, PQCC32 |
| CY7C421-65JI | 制造商:Cypress Semiconductor 功能描述:FIFO, 512 x 9, Asynchronous, 32 Pin, Plastic, PLCC |
| CY7C421-65PC | 制造商:Cypress Semiconductor 功能描述:FIFO, 512 x 9, Asynchronous, 28 Pin, Plastic, DIP |
| CY7C42165VC | 制造商:CYPRESS 功能描述:* |
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