參數(shù)資料
型號: CY7C4215V-25ASC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: SERIAL DTE CABLE WITH DB9 FEMALE CONNECTOR
中文描述: 512 X 18 OTHER FIFO, 15 ns, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, STQFP-64
文件頁數(shù): 10/25頁
文件大?。?/td> 409K
代理商: CY7C4215V-25ASC
CY7C4425/4205/4215
CY7C4225/4235/4245
10
Notes:
19. PAE offset – n. Number of data words into FIFO already = n.
20. PAE offset – n.
21. t
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the
rising RCLK is less than t
, then PAE may not change state until the next RCLK.
22. If a read is performed on this rising edge of the read clock, there will be Empty + (n – 1) words in the FIFO when PAE goes LOW.
Switching Waveforms
(continued)
t
ENH
Programmable Almost Empty Flag Timing
WCLK
PAE
]
REN
RCLK
t
CLKH
t
PAE
t
ENS
n+1
WORDS
IN FIFO
t
CLKL
t
ENS
t
PAE
n WORDS IN FIFO
42X5–13
[19]
WEN
Note
20
t
ENH
WCLK
PAE
RCLK
t
CLKH
t
ENS
t
CLKL
t
ENS
t
PAEsynch
N + 1 WORDS
INFIFO
42X5–14
t
ENH
t
ENS
t
ENH
t
ENS
t
PAEsynch
REN
WEN
WEN2
t
SKEW3
Note
22
Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)
[21]
相關PDF資料
PDF描述
CY7C4215V-35ASC SERIAL DTE CABLE WITH DB9 FEMALE CONNECTOR
CY7C4205-10AC 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4205-10AI 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4205-10ASC 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4205-10ASI 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
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