參數(shù)資料
型號: CY7C4215V-15ASC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: SERVSWITCH AFFINITY SERIADTE CABLE DB9F-10FT
中文描述: 512 X 18 OTHER FIFO, 11 ns, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, STQFP-64
文件頁數(shù): 7/25頁
文件大?。?/td> 409K
代理商: CY7C4215V-15ASC
CY7C4425/4205/4215
CY7C4225/4235/4245
7
Notes:
14. .t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the
rising edge of WCLK and the rising edge of RCLK is less than t
, then EF may not change state until the next RCLK edge.
15. The clocks (RCLK, WCLK) can be free-running during reset.
16. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
Switching Waveforms
(continued)
Read Cycle Timing
t
CLKH
t
CLKL
NO OPERATION
t
SKEW2
WEN
t
CLK
t
OHZ
t
REF
t
REF
RCLK
Q
0
–Q
17
EF
REN
WCLK
OE
t
OE
t
ENS
t
OLZ
t
A
t
ENH
VALID DATA
42X5–7
[14]
t
RS
t
RSR
Q
0 -
Q
17
RS
t
RSF
t
RSF
t
RSF
OE=1
OE=0
REN,WEN,
LD
EF,PAE
FF,PAF,
HF
42X5–8
Reset Timing
[15]
[16]
相關PDF資料
PDF描述
CY7C4215V-25ASC SERIAL DTE CABLE WITH DB9 FEMALE CONNECTOR
CY7C4215V-35ASC SERIAL DTE CABLE WITH DB9 FEMALE CONNECTOR
CY7C4205-10AC 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4205-10AI 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4205-10ASC 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
相關代理商/技術參數(shù)
參數(shù)描述
CY7C4215V-15ASXC 功能描述:先進先出 512 X18 LO VLTG SYNC 先進先出 COM RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
CY7C4215V-25ASC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C421-65AC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C421-65JC 制造商:Cypress Semiconductor 功能描述:512 X 9 OTHER FIFO, 65 ns, PQCC32
CY7C421-65JI 制造商:Cypress Semiconductor 功能描述:FIFO, 512 x 9, Asynchronous, 32 Pin, Plastic, PLCC