參數(shù)資料
型號(hào): CY7C4215-35JC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): DRAM
英文描述: 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
中文描述: 512 X 18 OTHER FIFO, 20 ns, PQCC68
封裝: PLASTIC, LCC-68
文件頁(yè)數(shù): 7/25頁(yè)
文件大小: 409K
代理商: CY7C4215-35JC
CY7C4425/4205/4215
CY7C4225/4235/4245
7
Notes:
14. .t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the
rising edge of WCLK and the rising edge of RCLK is less than t
, then EF may not change state until the next RCLK edge.
15. The clocks (RCLK, WCLK) can be free-running during reset.
16. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
Switching Waveforms
(continued)
Read Cycle Timing
t
CLKH
t
CLKL
NO OPERATION
t
SKEW2
WEN
t
CLK
t
OHZ
t
REF
t
REF
RCLK
Q
0
–Q
17
EF
REN
WCLK
OE
t
OE
t
ENS
t
OLZ
t
A
t
ENH
VALID DATA
42X5–7
[14]
t
RS
t
RSR
Q
0 -
Q
17
RS
t
RSF
t
RSF
t
RSF
OE=1
OE=0
REN,WEN,
LD
EF,PAE
FF,PAF,
HF
42X5–8
Reset Timing
[15]
[16]
相關(guān)PDF資料
PDF描述
CY7C4215-35JI 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4215-10AC 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4215-10AI 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4215-10ASC 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4215-10ASI 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
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