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參數(shù)資料
| 型號： | CY7C4215-25JC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| 中文描述： | 512 X 18 OTHER FIFO, 15 ns, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 1/25頁 |
| 文件大小： | 409K |
| 代理商： | CY7C4215-25JC |
64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs
fax id: 5410
CY7C4425/4205/4215
CY7C4225/4235/4245
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
April 1995 - Revised August 18, 1997
1CY7C4225
Features
High-speed, low-power, first-in first-out (FIFO)
memories
64 x 18 (CY7C4425)
256 x 18 (CY7C4205)
512 x 18 (CY7C4215)
1K x 18 (CY7C4225)
2K x 18 (CY7C4235)
4K x 18 (CY7C4245)
High-speed 100-MHz operation (10 ns read/write cycle
time)
Low power (I
CC
=45 mA)
Fully asynchronous and simultaneous read and write
operation
Empty, Full, Half Full, and Programmable Almost
Empty/Almost Full status flags
TTL-compatible
Retransmit function
Output Enable (OE) pin
Independent read and write enable pins
Center power and ground for reduced noise
Supports free-running 50% duty cycle clock inputs
Width Expansion Capability
Depth Expansion Capability
Space saving 64-pin 10x10 TQFP, and 14x14 TQFP
68-pin PLCC
Functional Description
T
he CY7C42X5 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 18 bits wide and are pin/functionally compatible to
IDT722x5. The CY7C42X5 can be cascaded to increase FIFO
depth. Programmable features include Almost Full/Almost
Empty flags. These FIFOs provide solutions for a wide variety
of data buffering needs, including high-speed data acquisition,
multiprocessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and a write enable
pin (WEN).
When WEN is asserted, data is written into the FIFO on the
rising edge of the WCLK signal. While WEN is held active, data
is continually written into the FIFO on each cycle. The output
port is controlled in a similar manner by a free-running read
clock (RCLK) and a read enable pin (REN). In addition, the
CY7C42X5 have an output enable pin (OE). The read and
write clocks may be tied together for single-clock operation or
the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI,
RXI), cascade output (WXO, RXO), and First Load (FL) pins.
The WXO and RXO pins are connected to the WXI and RXI
pins of the next device, and the WXO and RXO pins of the last
device should be connected to the WXI and RXI pins of the
first device. The FL pin of the first device is tied to V
SS
and the
FL pin of all the remaining devices should be tied to V
CC
.
The CY7C42X5 provides five status pins. These pins are de-
coded to determine one of five states: Empty, Almost Empty,
Half Full, Almost Full, and Full (see Table 2). The Half Full flag
shares the WXO pin. This flag is valid in the standalone and
width-expansion configurations. In the depth expansion, this
pin provides the expansion out (WXO) information that is used
to signal the next FIFO when it will be activated.
The Empty and Full flags are synchronous, i.e., they change
state relative to either the read clock (RCLK) or the write clock
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag archi-
tecture guarantees that the flags will remain valid from one
clock cycle to the next. As mentioned previously, the Almost
Empty/Almost Full flags become synchronous if the
V
CC
/SMODE is tied to V
SS
. All configurations are fabricated
using an advanced 0.65
μ
N-Well CMOS technology. Input
ESD protection is greater than 2001V, and latch-up is prevent-
ed by the use of guard rings.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C4215-25JI | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4215-35AC | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4215-35AI | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4215-35ASC | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4215-35ASI | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C4215V-15ASC | 功能描述:IC SYNC FIFO MEM 512X18 64LQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| CY7C4215V-15ASXC | 功能描述:先進(jìn)先出 512 X18 LO VLTG SYNC 先進(jìn)先出 COM RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| CY7C4215V-25ASC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C421-65AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C421-65JC | 制造商:Cypress Semiconductor 功能描述:512 X 9 OTHER FIFO, 65 ns, PQCC32 |
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