參數(shù)資料
型號: CY7C4205-10JI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
中文描述: 256 X 18 OTHER FIFO, 8 ns, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 6/25頁
文件大?。?/td> 409K
代理商: CY7C4205-10JI
CY7C4425/4205/4215
CY7C4225/4235/4245
6
t
PAFsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, V
CC
/SMODE tied to V
SS
)
Clock to Programmable Almost-Empty Flag
[12]
(Asynchronous mode, V
CC
/SMODE tied to V
CC
)
Clock to Programmable Almost-Full Flag
(Synchronous mode, V
CC
/SMODE tied to V
SS
)
Clock to Half-Full Flag
Clock to Expansion Out
Expansion in Pulse Width
Expansion in Set-Up Time
Skew Time between Read Clock and Write
Clock for Full Flag
Skew Time between Read Clock and Write
Clock for Empty Flag
Skew Time between Read Clock and Write
Clock for Programmable Almost Empty and Pro-
grammable Almost Full Flags.
8
10
15
20
ns
t
PAEasynch
12
16
20
25
ns
t
PAEsynch
8
10
15
20
ns
t
HF
t
XO
t
XI
t
XIS
t
SKEW1
12
7
16
10
20
15
25
20
ns
ns
ns
ns
ns
3
6.5
5
6
10
10
10
14
15
12
4.5
5
t
SKEW2
5
6
10
12
ns
t
SKEW3
10
15
18
20
ns
Switching Characteristics
Over the Operating Range (continued)
Parameter
Description
7C42X5-10
Min.
7C42X5-15
Min.
7C42X5-25
Min.
7C42X5-35
Min.
Max.
Max.
Max.
Max.
Unit
Switching Waveforms
Notes:
10. Pulse widths less than minimum values are not allowed.
11.
Values guaranteed by design, not currently tested.
12.
PAFasynch
, t
, after program register write will not be valid until 5 ns + t
.
13. t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the
rising edge of RCLK and the rising edge of WCLK is less than t
SKEW1
, then FF may not change state until the next WCLK edge.
Write Cycle Timing
t
CLKH
t
CLKL
NO OPERATION
t
DS
t
SKEW1
t
ENS
WEN
t
CLK
t
DH
t
WFF
t
WFF
t
ENH
WCLK
D
0
–D
17
FF
REN
RCLK
42X5–6
[13]
相關(guān)PDF資料
PDF描述
CY7C4205-15AC 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4205-15AI 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4205-15ASC 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4205-15ASI 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4205-15JC 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C4205-15AC 制造商:Cypress Semiconductor 功能描述:
CY7C4205-15ACT 制造商:Cypress Semiconductor 功能描述:
CY7C4205-15ASC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 256 x 18 64-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:256 X 18 68 PIN IDT COMPAT SYNC FIFO - Bulk
CY7C4205-15AXC 功能描述:IC SYNC FIFO MEM 256X18 64LQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256(64 x 4) 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP(0.300",7.62mm) 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
CY7C4205-15AXCT 功能描述:IC SYNC FIFO MEM 256X18 64LQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256(64 x 4) 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP(0.300",7.62mm) 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433