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參數(shù)資料
| 型號： | CY7C404-25DMB |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO |
| 中文描述： | 64 X 5 OTHER FIFO, 37 ns, CDIP18 |
| 封裝： | 0.300 INCH, CERDIP-18 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 270K |
| 代理商： | CY7C404-25DMB |
64 x 4 Cascadable FIFO
64 x 5 Cascadable FIFO
CY7C401/CY7C403
CY7C402/CY7C404
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
March 1986 – Revised April 1995
408-943-2600
1CY7C402
Features
64 x 4 (CY7C401 and CY7C403)
64 x 5 (CY7C402 and CY7C404)
High-speed first-in first-out memory (FIFO)
Processed with high-speed CMOS for optimum
speed/power
25-MHz data rates
50-ns bubble-through time—25 MHz
Expandable in word width and/or length
5-volt power supply
±
10% tolerance, both commercial
and military
Independent asynchronous inputs and outputs
TTL-compatible interface
Output enable function available on CY7C403 and
CY7C404
Capable of withstanding greater than 2001V electro-
static discharge
Pin compatible with MMI 67401A/67402A
Functional Description
The CY7C401 and CY7C403 are asynchronous first-in
first-out (FIFOs) organized as 64 four-bit words. The CY7C402
and CY7C404 are similar FIFOs organized as 64 five-bit
words. Both the CY7C403 and CY7C404 have an output en-
able (OE) function.
The devices accept 4- or 5-bit words at the data input (DI
0
–
DI
n
) under the control of the shift in (SI) input. The stored
words stack up at the output (DO
0
– DO
n
) in the order they
were entered. A read command on the shift out (SO) input
causes the next to last word to move to the output and all data
shifts down once in the stack. The input ready (IR) signal acts
as a flag to indicate when the input is ready to accept new data
(HIGH), to indicate when the FIFO is full (LOW), and to provide
a signal for a cascading. The output ready (OR) signal is a flag
to indicate the output contains valid data (HIGH), to indicate
the FIFO is empty (LOW), and to provide a signal for cascad-
ing.
Parallel expansion for wider words is accomplished by logical-
ly ANDing the IR and OR signals to form composite signals.
Serial expansion is accomplished by tying the data inputs of
one device to the data outputs of the previous device. The IR
pin of the receiving device is connected to the SO pin of the
sending device, and the OR pin of the sending device is con-
nected to the SI pin of the receiving device.
Reading and writing operations are completely asynchronous,
allowing the FIFO to be used as a buffer between two digital
machines of widely differing operating frequencies. The
25-MHz operation makes these FIFOs ideal for high-speed
communication and controller applications.
CY7C402
CY7C404
Logic Block Diagram
Pin Configurations
DIP
C401–1
C401–2
C401–3
1
2
3
4
5
6
7
8
12
11
10
9
13
16
15
14
(CY7C401) NC
(CY7C403) OE
IR
SI
DI
0
DI
1
DI
2
DI
3
GND
VCC
SO
OR
DO
0
DO
1
DO
2
DO
3
MR
20
4
5
6
7
8
3 2 1
19
18
17
16
15
14
910111213
SI
DI
0
DI
1
DI
2
NC
0
DO
1
DO
2
NC
DO
INPUT
CONTROL
LOGIC
SI
IR
DATAN
DI0
DI1
DI2
DI3
(DI4)
MASTER
RESET
MR
WRITE MULTIPLEXER
WRITE POINTER
READ MULTIPLEXER
READ POINTER
MEMORY
ARRAY
OUTPUT
CONTROL
LOGIC
DATAN
OUTPUT
ENABLE
OE
DO0
DO1
DO2
DO3
(DO4)
SO
OR
1
2
3
4
5
6
7
8
9
14
13
12
11
10
15
18
17
16
IR
SI
DI
0
DI
1
DI
2
DI
3
DI
4
GND
VCC
SO
OR
DO
0
DO
1
DO
2
DO
3
DO
4
MR
CY7C401
CY7C403
(CY7C404) OE
CY7C401
CY7C403
C401–4
20
4
5
6
7
8
3 2 1
19
18
17
16
15
14
910111213
C401–5
SI
DI
0
DI
1
DI
2
DI
3
0
DO
1
DO
2
DO
3
DO
CY7C402
CY7C404
LCC
LCC
DIP
Selection Guide
7C401/2–5
5
75
7C40X–10
10
75
90
7C40X–15
15
75
90
7C40X–25
25
75
90
Operating Frequency (MHz)
Maximum Operating
Current (mA)
Commercial
Military
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PDF描述 |
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| CY7C421-30LMB | CABLE ASSEMBLY; SMA MALE TO SMA FEMALE; 75 OHM, RG59B/U COAX |
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| CY7C425-25LMB | 256/512/1K/2K/4K x 9 Asynchronous FIFO |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C408A-15PC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C408A-15VC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C408A25DC | 制造商:CYPRESS 功能描述:* |
| CY7C408A25PC | 制造商:CYPRESS 功能描述:* |
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