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參數(shù)資料
| 型號(hào)： | CY7C401 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64 x 4 Cascadable FIFO(64 x 4 位級(jí)聯(lián)型先進(jìn)先出（FIFO）) |
| 中文描述： | 64 × 4級(jí)聯(lián)的FIFO（64 × 4位級(jí)聯(lián)型先進(jìn)先出（FIFO）的） |
| 文件頁(yè)數(shù)： | 3/13頁(yè) |
| 文件大?。?/td> | 224K |
| 代理商： | CY7C401 |
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CY7C401/CY7C403
CY7C402/CY7C404
3
AC Test Loads and Waveforms
C401–6
C401–7
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
≤
5 ns
≤
5 ns
OUTPUT
1.73V
C401–8
R1 437
R2
272
R2
272
R1 437
167
Equivalent to: THé VENIN EQUIVALENT
Switching Characteristics
Over the Operating Range
[2, 6]
Test
Conditions
Note 8
7C401–5
7C402–5
Min.
7C40X–10
Min.
7C40X–15
Min.
7C40X–25
[7]
Min.
Parameter
f
O
t
PHSI
t
PLSI
t
SSI
t
HSI
t
DLIR
t
DHIR
t
PHSO
t
PLSO
t
DLOR
t
DHOR
t
SOR
t
HSO
t
BT
t
SIR
t
HIR
t
PIR
t
POR
t
PMR
t
DSI
t
DOR
t
DIR
t
LZMR
t
OOE
t
HZOE
Notes:
6.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified I
OL
/I
OH
and 30-pF load
capacitance, as in part (a) of AC Test Loads and Waveforms.
7.
Commercial/Military
8.
I/f
O
> t
+ t
, I/f
> t
+ t
9.
t
SSI
and t
HSI
apply when memory is not full.
10. t
and t
apply when memory is full, SI is high and minimum bubble-through (t
) conditions exist.
11. All data outputs will be at LOW level after reset goes HIGH until data is entered into the FIFO.
12. HIGH-Z transitions are referenced to the steady-state V
OH
–500 mV and V
OL
+500 mV levels on the output. t
HZOE
is tested with 5-pF load capacitance as
in part (b) of AC Test Loads and Waveforms.
Description
Max.
5
Max.
10
Max.
15
Max.
25
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Operating Frequency
SI HIGH Time
SO LOW Time
Data Set-Up to SI
Data Hold from SI
Delay, SI HIGH to IR LOW
Delay, SI LOW to IR HIGH
SO HIGH Time
SO LOW Time
Delay, SO HIGH to OR LOW
Delay, SO LOW to OR HIGH
Data Set-Up to OR HIGH
Data Hold from SO LOW
Bubble-Through Time
Data Set-Up to IR
Data Hold from IR
Input Ready Pulse HIGH
Output Ready Pulse HIGH
MR Pulse Width
MR HIGH to SI HIGH
MR LOW to OR LOW
MR LOW to IR HIGH
MR LOW to Output LOW
Output Valid from OE LOW
Output High Z from OE HIGH
20
45
0
60
20
30
0
40
20
25
0
30
11
20
0
20
Note 9
Note 9
75
75
40
45
35
40
21/22
28/30
20
45
20
25
20
25
11
20
75
80
40
55
35
40
19/21
34/37
0
5
0
5
10
5
30
20
20
30
35
0
5
0
5
10
5
20
15
15
25
10
200
95
10
5
30
20
20
25
25
65
50/60
Note 10
Note 10
5
30
20
20
40
40
85
85
50
—
—
40
40
40
35
30
35
35
35
30
25
35
35
25
20
15
Note 11
Note 12
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C403 | 64 x 4 Cascadable FIFO(64 x 4 位級(jí)聯(lián)型先進(jìn)先出（FIFO）) |
| CY7C404 | 64 x 5 Cascadable FIFO(64 x 5位 級(jí)聯(lián)型先進(jìn)先出（FIFO）) |
| CY7C409A | 64 x 9 Cascadable FIFO(64 x 9位級(jí)聯(lián)型先進(jìn)先出（FIFO）) |
| CY7C408A | 64 x 8 Cascadable FIFO(64 x 8 位級(jí)聯(lián)型先進(jìn)先出（FIFO）) |
| CY7C4205 | 256 x 18 Synchronous FIFOs(256 x 18 同步 先進(jìn)先出) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C401-10PC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 64 x 4 16-Pin PDIP |
| CY7C401-15DC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C40115PC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C401-25PC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 64 x 4 16-Pin PDIP |
| CY7C403-10PC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 64 x 4 16-Pin PDIP |
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