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參數(shù)資料
| 型號(hào)： | CY7C373i |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | UltraLogic 64-Macrocell Flash CPLD(超邏輯的64 宏單元閃速 CPLD) |
| 中文描述： | UltraLogic 64宏單元CPLD的閃光（超邏輯的64個(gè)宏單元閃速的CPLD） |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大小： | 186K |
| 代理商： | CY7C373I |
CY7C373i
6
Switching Characteristics
Over the Operating Range
[11]
7C373i
–
125
7C373i
–
100
7C373i
–
83
7C373iL-83
7C373i
–
66
7C373iL
–
66
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Combinatorial Mode Parameters
Input to Combinatorial Output
[1]
t
PD
t
PDL
10
12
15
20
ns
Input to Output Through Transparent Input or
Output Latch
[1]
13
15
18
22
ns
t
PDLL
Input to Output Through Transparent Input and
Output Latches
[1]
Input to Output Enable
[1]
15
16
19
24
ns
t
EA
t
ER
Input Registered/Latched Mode Parameters
Clock or Latch Enable Input LOW Time
[7]
Clock or Latch Enable Input HIGH Time
[7]
14
16
19
24
ns
Input to Output Disable
14
16
19
24
ns
t
WL
t
WH
t
IS
t
IH
t
ICO
3
3
4
5
ns
3
3
4
5
ns
Input Register or Latch Set-Up Time
2
2
3
4
ns
Input Register or Latch Hold Time
2
2
3
4
ns
Input Register Clock or Latch Enable to
Combinatorial Output
[1]
14
16
19
24
ns
t
ICOL
Input Register Clock or Latch Enable to
Output Through Transparent Output Latch
[1]
16
18
21
26
ns
Output Registered/Latched Mode Parameters
Clock or Latch Enable to Output
[1]
t
CO
t
S
6.5
6.5
8
10
ns
Set-Up Time from Input to Clock or Latch
Enable
5.5
6
8
10
ns
t
H
t
CO2
Register or Latch Data Hold Time
0
0
0
0
ns
Output Clock or Latch Enable to Output Delay
(Through Memory Array)
[1]
14
16
19
24
ns
t
SCS
Output Clock or Latch Enable to Output Clock
or Latch Enable (Through Memory Array)
8
10
12
15
ns
t
SL
Set-Up Time from Input Through Transparent
Latch to Output Register Clock or Latch
Enable
10
12
15
20
ns
t
HL
Hold Time for Input Through Transparent Latch
from Output Register Clock or Latch Enable
0
0
0
0
ns
f
MAX1
Maximum Frequency with Internal Feedback
(Least of 1/t
SCS
, 1/(t
S
+ t
H
), or 1/t
CO
)
[7]
Maximum Frequency Data Path in Output
Registered/Latched Mode (Lesser of 1/(t
WL
+
t
WH
), 1/(t
S
+ t
H
), or 1/t
CO
)
[7]
Maximum Frequency of (2) CY7C373is with
External Feedback (Lesser of 1/(t
CO
+ t
S
) and
1/(t
WL
+ t
WH
)
[7]
Output Data Stable from Output clock Minus
Input Register Hold Time for 7C37x
[7, 12]
125
100
83
66
MHz
f
MAX2
153.8
153.8
125
100
MHz
f
MAX3
83.3
80
62.5
50
MHz
t
OH
–
t
IH
37x
0
0
0
0
ns
Notes:
11. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
12. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C373i. This specification is met
for the devices operating at the same ambient temperature and at the same power supply voltage.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C373I-100AI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C373I-100JC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells CMOS Technology 5V 84-Pin PLCC |
| CY7C373I-125AC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells CMOS Technology 5V 100-Pin TQFP |
| CY7C373I-66AC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells 5V 100-Pin TQFP |
| CY7C373I-66JC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells 5V 84-Pin PLCC 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells CMOS Technology 5V 84-Pin PLCC |
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