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參數(shù)資料
| 型號(hào)： | CY7C344 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Universal Synchronous EPLD(通用同步EPLD) |
| 中文描述： | 通用同步可編程邏輯器件（通用同步可編程邏輯器件） |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 95K |
| 代理商： | CY7C344 |
Multiple Array Matrix High-Density EPLDS
fax id: 6100
CY7C340 EPLD Family
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
December 1988 – Revised October 1995
1CY7C340
Family
EPLD
Features
Erasable, user-configurable CMOS EPLDs capable of
implementing high-density custom logic functions
0.8-micron double-metal CMOS EPROM technology
(CY7C34X)
Advanced 0.65-micron CMOS technology to increase
performance (CY7C34XB)
Multiple Array MatriX architecture optimized for speed,
density, and straightforward design implementation
—Programmable Interconnect Array (PIA) simplifies
routing
—Flexible macrocells increase utilization
—Programmable clock control
—Expander product terms implement complex logic
functions
Warp2
—Low-cost VHDL compiler for CPLDs and PLDs
—IEEE 1164-compliant VHDL
—Available on PC and Sun platforms
Warp3
—VHDL synthesis
—ViewLogic graphical user interface
—Schematic capture (ViewDraw)
—VHDL simulation (ViewSim)
—Available on PC and Sun platforms
General Description
The Cypress Multiple Array Matrix (MAX) family of EPLDs
provides a user-configurable, high-density solution to gener-
al-purpose logic integration requirements. With the combina-
Max Family Members
tion of innovative architecture and state-of-the-art process, the
MAX EPLDs offer LSI density without sacrificing speed.
The MAX architecture makes it ideal for replacing large
amounts of TTL SSI and MSI logic. For example, a 74161
counter utilizes only 3% of the 128 macrocells available in the
CY7C342B. Similarly, a 74151 8-to-1 multiplexer consumes
less than 1% of the over 1,000 product terms in the
CY7C342B. This allows the designer to replace 50 or more
TTL packages with just one MAX EPLD. The family comes in
a range of densities, shown below. By standardizing on a few
MAX building blocks, the designer can replace hundreds of
different 7400 series part numbers currently used in most dig-
ital systems.
The family is based on an architecture of flexible macrocells
grouped together into Logic Array Blocks (LABs). Within the
LAB is a group of additional product terms called expander
product terms. These expanders are used and shared by the
macrocells, allowing complex functions of up to 35 product
terms to be easily implemented in a single macrocell. A Pro-
grammable Interconnect Array (PIA) globally routes all signals
within devices containing more than one LAB. This architec-
ture is fabricated on the Cypress 0.8-micron, double-lay-
er-metal CMOS EPROM process, yielding devices with signif-
icantly higher integration, density and system clock speed than
the largest of previous generation EPLDs. The CY7C34XB de-
vices are 0.65-micron shrinks of the original 0.8-micron family.
The CY7C34XBs offer faster speed bins for each device in the
Cypress MAX family.
The density and performance of the CY7C340 family is ac-
cessed using Cypress’s Warp2 and Warp3design software.
Warp2 provides state-of-the-art VHDL synthesis for MAX
and F
LASH
370 at a very low cost. Warp3 s a sophisticated
CAE tool that includes schematic capture (ViewDraw) and
timing simulation (ViewSim) in addition to VHDL synthesis.
Consult the Warp2 and Warp3datasheets for more informa-
tion about the development tools.
Feature
CY7C344(B)
32
CY7C343(B)
64
CY7C342B
128
CY7C346(B)
128
CY7C341B
192
Macrocells
MAX Flip-Flops
MAX Latches
[1]
MAX Inputs
[2]
32
64
128
128
192
64
128
256
256
384
23
35
59
84
71
MAX Outputs
16
28
52
64
64
Packages
28H,J,W,P
44H,J
68H,J,R
84H,J 100R,N
84H,J,R
Key: P—Plastic DIP; H—Windowed Ceramic Leaded Chip Carrier; J—Plastic J-Lead Chip Carrier; R—Windowed Pin Grid Array;
W—Windowed Ceramic DIP; N—Plastic Quad Flat Pack
Notes:
1.
2.
PAL is a registered trademark of Advanced Micro Devices.
MAX is a registered trademark of Altera Corporation.
F
LASH
370 is a trademark of Cypress Semiconductor Corporation.
Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation.
ViewDraw and ViewSim are trademarks of ViewLogic Corp.
When all expander product terms are used to implement latches.
With one output.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C344-15JC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C344-15PC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 600 Gates 32 Macro Cells 0.8um Technology 5V 28-Pin PDIP |
| CY7C344-20JC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 600 Gates 32 Macro Cells 0.8um Technology 5V 28-Pin PLCC |
| CY7C344-20JI | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 600 Gates 32 Macro Cells 0.8um (CMOS) Technology 5V 28-Pin PLCC 制造商:Cypress Semiconductor 功能描述:Simple EPLD, Programmable Array Logic, 28 Pin, Plastic, PLCC |
| CY7C34420WC | 制造商:CYPRESS 功能描述:* |
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