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參數(shù)資料
| 型號： | CY7C343B-25JJI |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64-Macrocell MAX EPLD |
| 中文描述： | 64宏單元最大可編程邏輯器件 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 178K |
| 代理商： | CY7C343B-25JJI |
64-Macrocell MAX EPLD
CY7C343B
Cypress Semiconductor Corporation
Document #: 38-03038 Rev. **
3901 North First Street
San Jose
CA 95134
Revised December 8, 1999
408-943-2600
43B
Features
64 MAX macrocells in 4 LABs
8 dedicated inputs, 24 bidirectional I/O pins
Programmable interconnect array
Advanced 0.65-micron CMOS technology to increase
performance
Available in 44-pin HLCC, PLCC
Lowest power MAX device
Functional Description
The CY7C343B is a high-performance, high-density erasable
programmable logic device, available in 44-pin PLCC and
HLCC packages.
The CY7C343B contains 64 highly flexible macrocells and 128
expander product terms. These resources are divided into four
Logic Array Blocks (LABs) connected through the Program-
mable Inter-connect Array (PIA). There are 8 input pins, one
that doubles as a clock pin when needed. The CY7C343B also
has 28 I/O pins, each connected to a macrocell (6 for LABs A
and C, and 8 for LABs B and D). The remaining 36 macrocells
are used for embedded logic.
The CY7C343B is excellent for a wide range of both synchro-
nous and asynchronous applications.
MAX is a registered trademark of Altera Corporation.
MACROCELL17
MACROCELL18
MACROCELL19
MACROCELL20
MACROCELL21
MACROCELL22
MACROCELL23
MACROCELL24
MACROCELL38
MACROCELL37
MACROCELL36
MACROCELL35
MACROCELL34
MACROCELL33
9 INPUT
11 INPUT
12 INPUT
13 INPUT
P
I
A
MACROCELL1
MACROCELL2
MACROCELL3
MACROCELL4
MACROCELL5
MACROCELL6
MACROCELL56
MACROCELL55
MACROCELL54
MACROCELL53
MACROCELL52
MACROCELL51
MACROCELL50
MACROCELL49
MACROCELLS 7 - 16
MACROCELLS57 - 64
MACROCELLS 25 - 32
MACROCELLS39 - 48
INPUT35
INPUT/CLK34
INPUT33
INPUT31
2
4
5
6
7
8
1
44
42
41
40
39
38
37
30
29
28
27
26
24
SYSTEM CLOCK
(3, 14, 25, 36)
(10, 21, 32, 43)
V
CC
GND
LAB A
LAB B
LAB D
LAB C
C343B-1
Logic Block Diagram
DEDICATED
INPUTS
I/O PINS
15
16
17
18
19
20
22
23
I/O PINS
I/O PINS
I/O PINS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C343B-30JJI | 64-Macrocell MAX EPLD |
| CY7C343B-35HHI | 64-Macrocell MAX EPLD |
| CY7C343B-35JJI | 64-Macrocell MAX EPLD |
| CY7C343 | 64-Macrocell MAX EPLD |
| CY7C343-30HMB | 64-Macrocell MAX EPLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C343B-30JC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 1.25K Gates 64 Macro Cells 40MHz 0.65um Technology 5V 44-Pin PLCC |
| CY7C343B-35JI | 制造商:QP Semiconductor 功能描述: |
| CY7C344-15JC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C344-15PC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 600 Gates 32 Macro Cells 0.8um Technology 5V 28-Pin PDIP |
| CY7C344-20JC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 600 Gates 32 Macro Cells 0.8um Technology 5V 28-Pin PLCC |
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