型號: | CY7C342-40HI |
英文描述: | UV-Erasable/OTP Complex PLD |
中文描述: | UV-Erasable/OTP復(fù)雜可編程邏輯器件 |
文件頁數(shù): | 1/12頁 |
文件大?。?/td> | 858K |
代理商: | CY7C342-40HI |
相關(guān)PDF資料 |
PDF描述 |
---|---|
CY7C342-40HMB | UV-Erasable/OTP Complex PLD |
CY7C342-40JC | UV-Erasable/OTP Complex PLD |
CY7C342-40JI | UV-Erasable/OTP Complex PLD |
CY7C342-40RI | UV-Erasable/OTP Complex PLD |
CY7C342-40RMB | UV-Erasable/OTP Complex PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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CY7C342B-15HMB | 制造商:Cypress Semiconductor 功能描述:128-MACROCELL MAX EPLD |
cy7c342b-15jc | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 2.5K Gates 128 Macro Cells 83.3MHz 0.65um Technology 5V 68-Pin PLCC |
CY7C342B-20HMB | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 128 Macro Cells 33.3MHz 0.8um (CMOS) Technology 5V |
CY7C342B-25HC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 2.5K Gates 128 Macro Cells 50MHz 0.65um Technology 5V 68-Pin Windowed LCC |
CY7C342B-25HMB | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 128 Macro Cells 33.3MHz 0.8um (CMOS) Technology 5V |