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參數(shù)資料
| 型號(hào)： | CY7C341B-35RI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | UV PLD, 55 ns, CPGA84 |
| 封裝： | WINDOWED, PGA-84 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 339K |
| 代理商： | CY7C341B-35RI |
USE ULTRA37000 FOR
ALL NEW DESIGNS
CY7C341B
Document #: 38-03016 Rev. *C
Page 2 of 12
P
I
A
MACROCELL 1
MACROCELL 2
MACROCELL 3
MACROCELL 4
MACROCELL 5
MACROCELL 6
MACROCELL 7
MACROCELL 8
MACROCELL 97
MACROCELL 98
MACROCELL 99
MACROCELL 100
MACROCELL 101
MACROCELL 102
MACROCELL 103
MACROCELL 104
MACROCELL 9–16
MACROCELL 105–112
MACROCELL 17
MACROCELL 18
MACROCELL 19
MACROCELL 20
MACROCELL 113
MACROCELL 114
MACROCELL 115
MACROCELL 116
MACROCELL 21–32
MACROCELL 117–128
MACROCELL 33
MACROCELL 34
MACROCELL 35
MACROCELL 36
MACROCELL 129
MACROCELL 130
MACROCELL 131
MACROCELL 132
MACROCELL 37–48
MACROCELL 133–144
MACROCELL 49
MACROCELL 50
MACROCELL 51
MACROCELL 52
MACROCELL 145
MACROCELL 146
MACROCELL 147
MACROCELL 148
MACROCELL 53–64
MACROCELL 149–160
MACROCELL 65
MACROCELL 66
MACROCELL 67
MACROCELL 68
MACROCELL 161
MACROCELL 162
MACROCELL 163
MACROCELL 164
MACROCELL 69–80
MACROCELL 165–176
MACROCELL 81
MACROCELL 82
MACROCELL 83
MACROCELL 84
MACROCELL 85
MACROCELL 86
MACROCELL 87
MACROCELL 88
MACROCELL 177
MACROCELL 178
MACROCELL 179
MACROCELL 180
MACROCELL 181
MACROCELL 182
MACROCELL 183
MACROCELL 184
MACROCELL 89–96
MACROCELL 185–192
INPUT
(C6) 84
INPUT
(C7) 83
INPUT
(L7) 44
INPUT
(J7) 43
1 (A6)
INPUT/CLK
2 (A5)
INPUT
41 (K6)
INPUT
42 (J6)
INPUT
4(C5)
5(A4)
6(B4)
7(A3)
8(A2)
9(B3)
10
(A1)
11
(B2)
12 (C2)
13 (B1)
14 (C1)
15 (D2)
16
(D1)
17
(E3)
20
(F2)
21
(F3)
22 (G3)
23 (G1)
25
(F1)
26
(H1)
27
(H2)
28
(J1)
29
(K1)
30
(J2)
31
(L1)
32
(K2)
33
(K3)
34
(L2)
35
(L3)
36
(K4)
37
(L4)
38
(J5)
46 (L6)
47 (L8)
48 (K8)
49 (L9)
50 (L10)
51 (K9)
52 (L11)
53 (K10)
54 (J10)
55 (K11)
56 (J11)
57 (H10)
58 (H11)
59 (F10)
62 (G9)
63 (F9)
64 (F11)
65 (E11)
67 (E9)
68 (D11)
69 (D10)
70 (C11)
71 (B11)
72 (C10)
73 (A11)
74 (B10)
75 (B9)
76 (A10)
77 (A9)
78 (B8)
79 (A8)
80 (B6)
SYSTEMCLOCK
3, 24, 45, 66 (B5, G2, K7, E10)
18, 19, 39, 40, 60, 61, 81, 82 (E1, E2, K5, L5, G10, G11, A7, B7)
VCC
GND
() – PERTAIN TO 84-PIN PGA PACKAGE
LAB A
LAB B
LAB C
LAB D
LAB E
LAB F
LAB G
LAB H
LAB I
LAB J
LAB K
LAB L
Logic Block Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C341B-25HC | UV PLD, 40 ns, CQCC84 |
| CY7C341B-25HI | UV PLD, 40 ns, CQCC84 |
| CY7C341B-35HC | UV PLD, 55 ns, CQCC84 |
| CY7C341B-35HI | UV PLD, 55 ns, CQCC84 |
| CY7C343B-30JCT | OT PLD, 30 ns, PQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C342-25HC | 制造商:Cypress Semiconductor 功能描述:CMOS EPLD SMD 7C342 PLCC68 5V |
| CY7C342-30HC | 制造商:Cypress Semiconductor 功能描述: 制造商:Cypress Semiconductor 功能描述:Complex Erasable Programmable Logic Device, 128 Cell, 30ns, 68 Pin, Ceramic, PLCC |
| CY7C34235HMB | 制造商:CYPRESS 功能描述:New |
| CY7C342B-15HMB | 制造商:Cypress Semiconductor 功能描述:128-MACROCELL MAX EPLD |
| cy7c342b-15jc | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 2.5K Gates 128 Macro Cells 83.3MHz 0.65um Technology 5V 68-Pin PLCC |
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