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參數(shù)資料
| 型號(hào)： | CY7C335 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Universal Synchronous EPLD(通用同步EPLD) |
| 中文描述： | 通用同步可編程邏輯器件（通用同步可編程邏輯器件） |
| 文件頁數(shù)： | 1/17頁 |
| 文件大小： | 486K |
| 代理商： | CY7C335 |
Universal Synchronous EPLD
fax id: 6018
CY7C335
Cypress Semiconductor Corporation
3901 North First Street
San Jose
July 1991 – Revised March 26, 1997
CA 95134
408-943-2600
1CY7C335
Features
100-MHz output registered operation
Twelve I/O macrocells, each having:
—Registered, three-state I/O pins
—Input and output register clock select multiplexer
—Feed back multiplexer
—Output enable (OE) multiplexer
Bypass on input and output registers
All twelve macrocell state registers can be hidden
User configurable I/O macrocells to implement JK or
RS flip-flops and T or D registers
Input multiplexer per pair of I/O macrocells allows I/O
pin associated with a hidden macrocell state register
to be saved for use as an input
Four dedicated hidden registers
Twelve dedicated registered inputs with individually
programmable bypass option
Three separate clocks—two input clocks, two output
clocks
Common (pin 14-controlled) or product term-controlled
output enable for each I/O pin
256 product terms—32 per pair of macrocells, variable
distribution
Global, synchronous, product term-controlled, state
register set and reset—inputs to product term are
clocked by input clock
—2-ns input set-up and 9-ns output register clock to
output
—10-ns input register clock to state register clock
28-pin, 300-mil DIP, LCC, PLCC
Erasable and reprogrammable
Programmable security bit
Functional Description
The CY7C335 is a high-performance, erasable, programma-
ble logic device (EPLD) whose architecture has been opti-
mized to enable the user to easily and efficiently construct very
high performance state machines.
The architecture of the CY7C335, consisting of the user-con-
figurable output macrocell, bidirectional I/O capability, input
registers, and three separate clocks, enables the user to de-
sign high-performance state machines that can communicate
either with each other or with microprocessors over bidirec-
tional parallel buses of user-definable widths.
The four clocks permit independent, synchronous state ma-
chines to be synchronized to each other.
The user-configurable macrocells enable the designer to des-
ignate JK-, RS-, T-, or D-type devices so that the number of
product terms required to implement the logic is minimized.
The CY7C335 is available in a wide variety of packages in-
cluding 28-pin, 300-mil plastic and ceramic DIPs, PLCCs, and
LCCs.
Logic Block Diagram
C335–1
14
13
12
11
10
9
7
6
5
4
3
2
1
8
15
16
17
18
19
20
23
24
25
26
27
28
22
21
V
SS
V
CC
PROGRAMMABLE AND ARRAY
(258x68)
17
11
15
13
19
9
11
17
9
19
13
15
13
17
11
19
I/O
11
I/O
10
I/O
9
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
V
SS
I
5
OE/I
11
I
10
I
9
I
8
I
7
I
6
I
4
I
3
I
2
I
1
/CLK3
I
0
/CLK2
CLK1
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