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參數(shù)資料
| 型號： | CY7C271A-45WC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 32K x 8 Power Switched and Reprogrammable PROM |
| 中文描述： | 32K X 8 UVPROM, 45 ns, CDIP28 |
| 封裝： | 0.300 INCH, WINDOWED, CERDIP-28 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 167K |
| 代理商： | CY7C271A-45WC |
32K x 8 Power Switched and
Reprogrammable PROM
CY7C271A
Cypress Semiconductor Corporation
Document #: 38-04013 Rev. *B
3901 North First Street
San Jose
CA 95134
Revised December 28, 2002
408-943-2600
1CY7C271A
Features
CMOS for optimum speed/power
Windowed for reprogrammability
High speed
—25 ns (Commercial)
Low power
—275 mW (Commercial)
Super low standby power
—Less than 85 mW when deselected
EPROM technology 100%programmable
Slim 300-mil package
Direct replacement for bipolar PROMs
Capable of withstanding >4001V static discharge
Functional Description
The CY7C271A is a high-performance 32,768-word by 8-bit
CMOS PROM. When disabled (CE HIGH), the 7C271A
automatically powers down into a low-power stand-by mode.
The CY7C271A is packaged in the 300-mil slim package and
is available in a cerDIP package equipped with an erasure
window to provide for reprogrammability. When exposed to UV
light, the PROM is erased and can be reprogrammed. The
memory cells utilize proven EPROM floating gate technology
and byte-wide intelligent programming algorithms.
The CY7C271A offers the advantages of lower power,
superior performance, and programming yield. The EPROM
cell requires only 12.5V for the super voltage, and low current
requirements allow for gang programming. The EPROM cells
allow each memory location to be tested 100% because each
location is written into, erased, and repeatedly exercised prior
to encapsulation. Each PROM is also tested for AC perfor-
mance to guarantee that after customer programming, the
product will meet DC and AC specification limits.
Reading the 7C271A is accomplished by placing active LOW
signals on CS
1
and CE, and an active HIGH on CS
2
. The
contents of the memory location addressed by the address
lines (A
0
–A
14
) will become available on the output lines
(O
0
–O
7
).
Logic BlockDiagram
Pin Configurations
DIP/Flatpack
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
17
18
19
20
24
23
22
21
25
28
27
26
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
V
CC
A
10
A
11
A
12
A
13
A
14
CS
1
CS
2
CE
O
7
O
6
O
5
O
4
O
3
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
POWER-DOWN
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
CE
CS
1
CS
2
256 x 1024
PROARRAY
8 x 1 OF 128
A
13
A
9
A
14
Y
X
ADDRESS
ADDRESS
28
4
5
6
7
8
9
10
1112
3 2 1
27
13
26
25
24
23
22
21
20
19
A
VC
G
A
A
O
O
O
0
18
O
O
NC
A
0
A
4
A
3
A
2
A
1
E
CLR
E
S
CP
NC
O
7
O
6
N
N
O
A
P
PLCC
Top View
14151617
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| CY7C271A-55PC | 制造商:Cypress Semiconductor 功能描述:EPROM OTP 256K-Bit 32K x 8 55ns 28-Pin PDIP |
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| CY7C274-55PC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
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