參數(shù)資料
型號: CY7C225A-40LMB
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 324 POS 1MM PITCH BGA SOCKET
中文描述: 512 X 8 OTPROM, 25 ns, CQCC28
封裝: LCC-28
文件頁數(shù): 1/9頁
文件大?。?/td> 186K
代理商: CY7C225A-40LMB
512 x 8 Registered PROM
CY7C225A
Cypress Semiconductor Corporation
Document #: 38-04001 Rev. *B
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised October 8, 2002
1CY7C225A
Features
CMOS for optimum speed/power
High speed
—25 ns address set-up
—12 ns clock to output
Low power
—495 mW (Commercial)
—660 mW (Military)
Synchronous and asynchronous output enables
On-chip edge-triggered registers
Buffered common PRESET and CLEAR inputs
EPROM technology, 100% programmable
Slim 300-mil, 24-pin plastic or hermetic DIP, 28-pin LCC,
or 28-pin PLCC
5V
±
10% V
CC
, commercial and military
TTL-compatible I/O
Direct replacement for bipolar PROMs
Logic Block Diagram
Capable of withstanding greater than 2001V static
discharge
Functional Description
The CY7C225A is a high-performance 512-word by 8-bit
electrically programmable read only memory packaged in a
slim 300-mil plastic or hermetic DIP, 28-pin leadless chip
carrier, and 28-pin PLCC. The memory cells utilize proven
EPROM floating gate technology and byte-wide intelligent
programming algorithms.
The CY7C225A replaces bipolar devices and offers the advan-
tages of lower power, superior performance, and high
programming yield. The EPROM cell requires only 12.5V for
the supervoltage and low current requirements allow for gang
programming. The EPROM cells allow for each memory
location to be tested 100%, as each location is written into,
erased, and repeatedly exercised prior to encapsulation. Each
PROM is also tested for AC performance to guarantee that
after customer programming the product will meet AC specifi-
cation limits.
Pin Configurations
DIP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
V
CC
A
8
PS
E
CLR
E
S
CP
O
7
O
6
O
5
O
4
O
3
PROGRAMMABLE
ARRAY
MULTIPLEXER
15
8-BIT
EDGE-
TRIGGERED
REGISTER
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
PS
CLR
S
R
CP
CP
E
S
E
28
4
5
6
7
8
9
10
1112
3 2 1
27
13
26
25
24
23
22
21
20
19
A
VC
G
A
A
O
O
O
0
18
O
O
NC
A
0
A
4
A
3
A
2
A
1
E
CLR
E
S
CP
NC
O
7
O
6
N
N
O
A
P
LCC/PLCC
Top View
ADDRESS
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
8
A
7
COLUMN
ADDRESS
ROW
ADDRESS
14151617
Selection Guide
7C225A-25
25
12
90
7C225A-30
30
15
90
7C225A-40
40
25
Unit
ns
ns
mA
mA
Minimum Address Set-Up Time
Maximum Clock to Output
Maximum Operating
Current
Commercial
Military
120
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