參數(shù)資料
型號: CY7C167A-20VC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 16K x 1 Static RAM
中文描述: 16K X 1 STANDARD SRAM, 20 ns, PDSO20
封裝: 0.300 INCH, PLASTIC, SOJ-20
文件頁數(shù): 1/9頁
文件大?。?/td> 140K
代理商: CY7C167A-20VC
16K x 1 Static RAM
CY7C167A
Cypress Semiconductor Corporation
Document #: 38-05027 Rev. **
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised August 24, 2001
67A
Features
Automatic power-down when deselected
CMOS for optimum speed/power
High speed
—15 ns
Low active power
—495 mW
Low standby power
—220 mW
TTL-compatible inputs and outputs
Capable of withstanding greater than 2001V electro-
static discharge
V
IH
of 2.2V
Functional Description
The CY7C167A is a high-performance CMOS static RAM or-
ganized as 16,384 words by 1 bit. Easy memory expansion is
provided by an active LOW Chip Enable (CE) and three-state
drivers. The CY7C167A has an automatic power-down fea-
ture, reducing the power consumption by 67% when
deselected.
Writing to the device is accomplished when the Chip Select
(CE) and Write Enable (WE) inputs are both LOW. Data on the
input pin (DI) is written into the memory location specified on
the address pins (A
0
through A
13
).
Reading the device is accomplished by taking the Chip Enable
(CE) LOW, while (WE) remains HIGH. Under these conditions,
the contents of the location specified on the address pins will
appear on the data output (DO) pin.
The output pin remains in a high-impedance state when Chip
Enable is HIGH, or Write Enable (WE) is LOW.
A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configuration
128 x 128
ARRAY
C167A-1
Top View
DIP
A
1
A
2
A
3
A
4
A
5
A
6
A
0
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
CE
DO
DI
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18
17
16
15
7C167A
A
1
A
2
A
3
A
4
A
5
A
6
DO
WE
CE
GND
V
CC
A
13
A
12
A
11
A
10
A
9
A
8
A
7
DI
C167A-2
A
0
20
19
Selection Guide
7C167A-15
15
90
7C167A-20
20
90
7C167A-25
25
90
7C167A-35
35
90
7C167A-45
45
90
Maximum Access Time (ns)
Maximum Operating Current (mA)
相關(guān)PDF資料
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