- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379089 > CY7C1527V18-200BZXI (CYPRESS SEMICONDUCTOR CORP) 72-Mbit DDR-II SRAM 2-Word Burst Architecture PDF資料下載
參數(shù)資料
| 型號： | CY7C1527V18-200BZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| 中文描述： | 8M X 9 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 1/28頁 |
| 文件大?。?/td> | 457K |
| 代理商： | CY7C1527V18-200BZXI |
當前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
72-Mbit DDR-II SRAM 2-Word
Burst Architecture
CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Cypress Semiconductor Corporation
Document #: 38-05563 Rev. *D
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised June 1, 2006
Features
72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
300-MHz clock for high bandwidth
2-Word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) @ 300 MHz
Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches
Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
Synchronous internally self-timed writes
1.8V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4V–V
DD
)
Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
Offered in both lead-free and non lead-free packages
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1516V18 – 8M x 8
CY7C1527V18 – 8M x 9
CY7C1518V18 – 4M x 18
CY7C1520V18 – 2M x 36
Functional Description
The CY7C1516V18, CY7C1527V18, CY7C1518V18, and
CY7C1520V18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry
and a 1-bit burst counter. Addresses for Read and Write are
latched on alternate rising edges of the input (K) clock.Write
data is registered on the rising edges of both K and K. Read
data is driven on the rising edges of C and C if provided, or on
the rising edge of K and K if C/C are not provided. Each
address location is associated with two 8-bit words in the case
of CY7C1516V18 and two 9-bit words in the case of
CY7C1527V18 that burst sequentially into or out of the device.
The burst counter always starts with a “0” internally in the case
of CY7C1516V18 and CY7C1527V18. On CY7C1518V18 and
CY7C1520V18, the burst counter takes in the least significant
bit of the external address and bursts two 18-bit words in the
case of CY7C1518V18 and two 36-bit words in the case of
CY7C1520V18 sequentially into or out of the device.
Asynchronous inputs include output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need for
separately capturing data from each individual DDR SRAM in
the system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
300 MHz
300
900
278 MHz
278
860
250 MHz
250
800
200 MHz
200
700
167 MHz
167
650
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current (x36)
[+] Feedback
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1527V18-250BZC | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1527V18-250BZI | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1527V18-250BZXC | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1527V18-278BZC | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1527V18-278BZI | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1543KV18-400BZC | 功能描述:靜態(tài)隨機存取存儲器 72MB (4Mx18) 1.8v 400MHz QDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1543KV18-400BZI | 功能描述:靜態(tài)隨機存取存儲器 72MB (4Mx18) 1.8v 400MHz QDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1543KV18-450BZC | 功能描述:靜態(tài)隨機存取存儲器 4Mb x 18 450 MHz RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1543KV18-450BZI | 功能描述:靜態(tài)隨機存取存儲器 72MB (8Mx9) 1.8v 450MHz QDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1543V18-333BZC | 功能描述:靜態(tài)隨機存取存儲器 72M Q2+ B4 (2.0) RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。