- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379088 > CY7C1527V18-200BZI (CYPRESS SEMICONDUCTOR CORP) 72-Mbit DDR-II SRAM 2-Word Burst Architecture PDF資料下載
參數(shù)資料
| 型號(hào)： | CY7C1527V18-200BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| 中文描述： | 8M X 9 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁(yè)數(shù)： | 22/28頁(yè) |
| 文件大?。?/td> | 457K |
| 代理商： | CY7C1527V18-200BZI |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)當(dāng)前第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)
CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Document #: 38-05563 Rev. *D
Page 22 of 28
Switching Characteristics
Over the Operating Range
[23, 24]
Cypress
Parameter
t
POWER
Consortium
Parameter
Description
300 MHz
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
1
–
1
–
1
278 MHz
250 MHz
200 MHz
167 MHz
Unit
ms
V
DD
(Typical) to the first
Access
[25]
K Clock and C Clock Cycle
Time
–
1
–
1
–
t
CYC
t
KHKH
3.30 5.25
3.60
5.25
4.0
6.3
5.0
7.9
6.0
8.4
ns
t
KH
t
KHKL
Input Clock (K/K and C/C)
HIGH
Input Clock (K/K and C/C)
LOW
K Clock Rise to K Clock Rise
and C to C Rise (rising edge
to rising edge)
K/K Clock Rise to C/C Clock Rise
(rising edge to rising edge)
1.32
–
1.4
–
1.6
–
2.0
–
2.4
–
ns
t
KL
t
KLKH
1.32
–
1.4
–
1.6
–
2.0
–
2.4
–
ns
t
KHKH
t
KHKH
1.49
–
1.6
–
1.8
–
2.2
–
2.7
–
ns
t
KHCH
t
KHCH
0.00 1.45
0.0
1.55
0.0
1.8
0.0
2.2
0.0
2.7
ns
Set-up Times
t
SA
t
AVKH
Address Set-up to K Clock
Rise
Control Set-up to K Clock
Rise (LD, R/W)
Double Data Rate Control
Set-up to Clock (K/K) Rise
(BWS
0
, BWS
1
, BWS
2
,
BWS
3
)
D
[X:0]
Set-up to Clock
(K/K) Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
SC
t
IVKH
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
SCDDR
t
IVKH
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
t
SD[26]
t
DVKH
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Hold Times
t
HA
t
KHAX
Address Hold after K Clock
Rise
Control Hold after K Clock
Rise (LD, R/W)
Double Data Rate Control
Hold after Clock (K/K) Rise
(BWS
0
, BWS
1
, BWS
2
,
BWS
3
)
D
[X:0]
Hold after Clock
(K/K) Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
t
HC
t
KHIX
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
HCDDR
t
KHIX
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
t
HD
t
KHDX
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Output Times
t
CO
t
CHQV
C/C Clock Rise (or K/K in single
clock mode) to Data Valid
Data Output Hold after
Output C/C Clock Rise
(Active to Active)
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
t
DOH
t
CHQX
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
t
CCQO
t
CHCQV
C/C Clock Rise to Echo
Clock Valid
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
Notes:
24.All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
25.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
minimum initially before a read or write operation
can be initiated.
26.For DQ0 data signal on CY7C1527V18 device, t
SD
is 0.5ns for 200MHz, 250MHz, 278MHz and 300MHz frequencies.
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1527V18-200BZXC | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1516V18-300BZI | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1516V18-300BZXC | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1516V18-300BZXI | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1518V18-167BZC | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1543KV18-400BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 72MB (4Mx18) 1.8v 400MHz QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1543KV18-400BZI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 72MB (4Mx18) 1.8v 400MHz QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1543KV18-450BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 4Mb x 18 450 MHz RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1543KV18-450BZI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 72MB (8Mx9) 1.8v 450MHz QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1543V18-333BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 72M Q2+ B4 (2.0) RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。