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參數(shù)資料
| 型號(hào)： | CY7C1523V18 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata |
| 中文描述： | RAM9 QDR-I/DDR-I/QDR-II/DDR-二勘誤表 |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大小： | 217K |
| 代理商： | CY7C1523V18 |
Document #: 001-06217 Rev. *C
Page 6 of 8
This issue only affects the EXTEST command when the device is in the JTAG mode. The normal functionality
of the device will not be affected.
TRIGGER CONDITION(S)
EXTEST command executed immediately after power-up without providing any K clock cycles.
SCOPE OF IMPACT
This issue only impacts the EXTEST command when device is tested in the JTAG mode. Normal functionality
of the device is not affected.
EXPLANATION OF ISSUE
Impedance matching circuitry (ZQ) is present on the QDR/DDR devices to set the desired impedance on the
outputs. This ZQ circuitry is updated every 1000 clock cycles of K clock to ensure that the impedance of the
O/P is set to valid state. However, when the device is operated in the JTAG mode immediately after power-
up, high frequency noise on the input K clock can be treated by the ZQ circuitry as valid clocks thereby setting
the outputs in to a high-impedance mode. If a minimum of 1000 valid K clocks are applied before performing
the JTAG test, this should clear the ZQ circuitry and ensure that the outputs are driven to valid impedance
levels.
WORKAROUND
Elimination of the issue: After power-up, before any valid operations are performed on the device, insert a
minimum of 1000 valid clocks on K input.
FIX STATUS
The fix involved bypassing the ZQ circuitry in JTAG mode. This was done by overriding the ZQ circuitry by the
JTAG signal. The fix has been implemented on the new revision and is now available. The new revision is an
increment of the existing revision. Please refer to Table 4 for the list of devices affected, current revision and
the new revision after the fix..
Table 4. List of Affected devices and the new revision
Current Revision
CY7C129*DV18
CY7C130*DV25
CY7C130*BV18
CY7C130*BV25
CY7C132*BV25
CY7C131*BV18
CY7C132*BV18
CY7C139*BV18
CY7C191*BV18
CY7C141*AV18
CY7C142*AV18
CY7C151*V18
CY7C152*V18
New Revision after the Fix
CY7C129*EV18
CY7C130*EV25
CY7C130*CV18
CY7C130*CV25
CY7C132*CV25
CY7C131*CV18
CY7C132*CV18
CY7C139*CV18
CY7C191*CV18
CY7C141*BV18
CY7C142*BV18
CY7C151*AV18
CY7C152*AV18
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1392BV18 | RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata |
| CY7C1393BV18 | RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata |
| CY7C1394BV18 | RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata |
| CY7C1411AV18 | RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata |
| CY7C1413AV18 | RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1523V18-167BZCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 1.8V 72MBIT 4MX18 0.5NS 165FBGA - Bulk |
| CY7C1523V18-200BZCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Bulk |
| CY7C1523V18-250BZCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Bulk |
| CY7C1523V18-250BZIES | 制造商:Cypress Semiconductor 功能描述:4MX18 72M DDR-II SIO BURST 2 SRAM - Bulk |
| CY7C1523V18-300BZC | 制造商:Cypress Semiconductor 功能描述:72MB (4MX18) DDR-II SRAM, 1.8V, 2WB, SIO - Bulk |
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