參數(shù)資料
型號: CY7C1522AV18-250BZC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
中文描述: 8M X 8 DDR SRAM, 0.45 ns, PBGA165
封裝: 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù): 7/28頁
文件大小: 1133K
代理商: CY7C1522AV18-250BZC
PRELIMINARY
CY7C1522AV18
CY7C1529AV18
CY7C1523AV18
CY7C1524AV18
Document #: 001-06981 Rev. *B
Page 7 of 28
CQ
Echo Clock
CQ is referenced with respect to C
. This is a free running clock and is synchronized to the
Input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC timing table.
CQ is referenced with respect to C
. This is a free-running clock and is synchronized to the
Input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC timing table.
Output Impedance Matching Input
. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to
V
DDQ
, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
DLL Turn Off - Active LOW
. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
For normal operation, this pin can be connected to a pull-up through a 10-Kohm or less pull-up
resistor. The device will behave in DDR-I mode when the DLL is turned off. In this mode, the
device can be operated at a frequency of up to 167 MHz with DDR-I timing.
TDO for JTAG
.
TCK pin for JTAG
.
TDI pin for JTAG
.
TMS pin for JTAG
.
Address expansion for 144M
. Can be tied to any voltage level.
Address expansion for 288M
. Can be tied to any voltage level.
Reference Voltage Input
. Static input used to set the reference level for HSTL inputs and
Outputs as well as AC measurement points.
Power supply inputs to the core of the device
.
Ground for the device
.
Power supply inputs for the outputs of the device
.
Not connected to the die
. Can be tied to any voltage level.
CQ
Echo Clock
ZQ
Input
DOFF
Input
TDO
TCK
TDI
TMS
V
SS
/144M
V
SS
/288M
V
REF
Output
Input
Input
Input
Input
Input
Input-
Reference
Power Supply
Ground
Power Supply
N/A
V
DD
V
SS
V
DDQ
NC
Pin Definitions
(continued)
Pin Name
I/O
Pin Description
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相關(guān)PDF資料
PDF描述
CY7C1522AV18-250BZI 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522AV18-250BZXC 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522AV18-250BZXI 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1523AV18-300BZC 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1523AV18-300BZI 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
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