參數資料
型號: CY7C1522AV18-200BZXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
中文描述: 8M X 8 DDR SRAM, 0.45 ns, PBGA165
封裝: 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁數: 9/28頁
文件大小: 1133K
代理商: CY7C1522AV18-200BZXC
PRELIMINARY
CY7C1522AV18
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CY7C1523AV18
CY7C1524AV18
Document #: 001-06981 Rev. *B
Page 9 of 28
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. During power-up, when the DOFF is tied HIGH, the
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K
for a minimum of 30 ns. However, it is not necessary for the
DLL to be specifically reset in order to lock the DLL to the
desired frequency. The DLL will automatically lock 1024 clock
cycles after a stable clock is presented.the DLL may be
disabled by applying ground to the DOFF pin. When the DLL
is turned off, the device will behave in DDR-I mode (with one
cycle latency and a longer access time). For information refer
to
the
application
note
QDRII/DDRII”.
Application Example
[2]
“DLL
Considerations
in
Truth Table
[3, 4, 5, 6, 7, 8]
Operation
K
LD
L
R/W
L
DQ
DQ
Write Cycle:
Load address; wait one cycle; input write data on
consecutive K and K rising edges.
Read Cycle:
Load address; wait one and a half cycle; read data
on consecutive C and C rising edges.
NOP: No Operation
Standby: Clock Stopped
L-H
D(A + 0) at K(t + 1)
D(A + 1) at K(t + 1)
L-H
L
H
Q(A + 0) at C(t + 1)
Q(A + 1) at C(t + 2)
L-H
H
X
X
X
High-Z
Previous State
High-Z
Previous State
Stopped
Notes:
2. The above application shows four DDR-II SIO being used.
3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
represents rising edge.
4. Device will power-up deselected and the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
6. “t” represents the cycle at which a Read/Write operation is started. t+1, t + 2 and t +3 are the first, second and third clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
8. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
LD
#
#
#
#
B
W
#
#
Vt = V
REF
C C#
CQ
CQ#
K#
ZQ
Q
D
K
C
C# K
BUS
MASTER
(CPU
or
ASIC)
SRAM 1
SRAM 4
DATA IN
DATA OUT
Address
LD#
R/W#
BWS#
SRAM 1 Input CQ
SRAM 1 Input CQ#
SRAM 4 Input CQ
SRAM 4 Input CQ#
Source K
Source K#
Delayed K
Delayed K#
R = 50
Ohms
R = 250
Ohms
CQ
CQ#
K#
ZQ
Q
LD
R/W
B
W
S
LD
#
R/W
#
Vt
Vt
Vt
R
R
R
A
A
D
R = 250
Ohms
B
W
S
#
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PDF描述
CY7C1522AV18-200BZXI 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522AV18-250BZC 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522AV18-250BZI 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522AV18-250BZXC 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522AV18-250BZXI 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
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