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參數(shù)資料
| 型號(hào)： | CY7C1520V18-250BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| 中文描述： | 2M X 36 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 457K |
| 代理商： | CY7C1520V18-250BZC |
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CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Document #: 38-05563 Rev. *D
Page 10 of 28
Write Cycle Descriptions
(CY7C1516V18 and CY7C1518V18)
[3, 9]
BWS
0
, NWS
0
L
BWS
1
, NWS
1
L
K
K
Comments
L-H
–
During the Data portion of a Write sequence
:
CY7C1516V18
both nibbles (D
[7:0]
) are written into the device,
CY7C1518V18
both bytes (D
[17:0]
) are written into the device.
During the Data portion of a Write sequence
:
CY7C1516V18
both nibbles (D
[7:0]
) are written into the device,
CY7C1518V18
both bytes (D
[17:0]
) are written into the device.
During the Data portion of a Write sequence
:
CY7C1516V18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will remain unaltered,
CY7C1518V18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will remain unaltered.
During the Data portion of a Write sequence
:
CY7C1516V18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will remain unaltered,
CY7C1518V18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will remain unaltered.
During the Data portion of a Write sequence
:
CY7C1516V18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will remain unaltered,
CY7C1518V18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will remain unaltered.
During the Data portion of a Write sequence
:
CY7C1516V18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will remain unaltered,
CY7C1518V18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will remain unaltered.
No data is written into the devices during this portion of a Write operation.
No data is written into the devices during this portion of a Write operation.
L
L
–
L-H
L
H
L-H
–
L
H
–
L-H
H
L
L-H
–
H
L
–
L-H
H
H
H
H
L-H
–
–
L-H
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1520V18-250BZI | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1520V18-250BZXC | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1520V18-250BZXI | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1520V18-278BZC | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1520V18-278BZI | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1520V18-250BZCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 1.8V 72MBIT 2MX36 0.45NS 165FBGA - Bulk |
| CY7C1520V18-300BZC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 1.8V 72MBIT 2MX36 0.45NS 165FBGA - Bulk |
| CY7C1520XC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1520YC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1520ZC | 制造商:Cypress Semiconductor 功能描述: |
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