參數(shù)資料
型號(hào)： CY7C1520V18-200BZXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 72-Mbit DDR-II SRAM 2-Word Burst Architecture
中文描述： 2M X 36 DDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 457K
代理商： CY7C1520V18-200BZXI
CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Document #: 38-05563 Rev. *D
Page 7 of 28
CQ
Output-
Clock
CQ is referenced with respect to C
. This is a free running clock and is synchronized to the Input
clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to
K. The timings for the echo clocks are shown in the AC Timing table.
CQ
Output-
Clock
CQ is referenced with respect to C
. This is a free running clock and is synchronized to the Input
clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to
K. The timings for the echo clocks are shown in the AC Timing table.
Output Impedance Matching Input
. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to
V
DDQ
, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
DLL Turn Off - active LOW
. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
TDO for JTAG
.
TCK pin for JTAG
.
TDI pin for JTAG
.
TMS pin for JTAG
.
Not connected to the die
. Can be tied to any voltage level.
Address expansion for 144M
. Can be tied to any voltage level.
Address expansion for 288M
. Can be tied to any voltage level.
Reference Voltage Input
. Static input used to set the reference level for HSTL inputs and Outputs
as well as AC measurement points.
Power Supply
Power supply inputs to the core of the device
.
Ground
Ground for the device
.
Power Supply
Power supply inputs for the outputs of the device
.
ZQ
Input
DOFF
Input
TDO
TCK
TDI
TMS
NC
V
SS
/144M
V
SS
/288M
V
REF
Output
Input
Input
Input
N/A
Input
Input
Input-
Reference
V
DD
V
SS
V
DDQ
Pin Definitions
(continued)
Pin Name
I/O
Pin Description
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1520V18-250BZC 72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1520V18-250BZI 72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1520V18-250BZXC 72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1520V18-250BZXI 72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1520V18-278BZC 72-Mbit DDR-II SRAM 2-Word Burst Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1520V18-225BZC 制造商:Cypress Semiconductor 功能描述:2MX36 72M DDR-II BURST 2 SRAM - Bulk
CY7C1520V18-250BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2M x 36 1.8V DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1520V18-250BZCES 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 1.8V 72MBIT 2MX36 0.45NS 165FBGA - Bulk
CY7C1520V18-300BZC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 1.8V 72MBIT 2MX36 0.45NS 165FBGA - Bulk
CY7C1520XC 制造商:Cypress Semiconductor 功能描述:
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