參數(shù)資料
型號(hào)： CY7C1520V18-200BZI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 72-Mbit DDR-II SRAM 2-Word Burst Architecture
中文描述： 2M X 36 DDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁(yè)數(shù)： 19/28頁(yè)
文件大?。?/td> 457K
代理商： CY7C1520V18-200BZI
CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Document #: 38-05563 Rev. *D
Page 19 of 28
Power-Up Sequence in DDR-II SRAM
[14, 15]
DDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power-Up Sequence
Apply power and drive DOFF LOW (All other inputs can be
HIGH or LOW)
— Apply V
DD
before V
DDQ
— Apply V
DDQ
before V
REF
or at the same time as V
REF
After the power and clock (K, K, C, C) are stable take DOFF
HIGH
The additional 1024 cycles of clocks are required for the
DLL to lock.
Power-up Waveforms
DLL Constraints
DLL uses either K or C clock as its synchronizing input.The
input should have low phase jitter, which is specified as
t
KC Var
.
The DLL will function at frequencies down to 80 MHz.
If the input clock is unstable and the DLL is enabled, then
the DLL may lock to an incorrect frequency, causing
unstable SRAM behavior
.
Notes:
14.It is recommended that the DOFF pin be pulled HIGH via a pull up resistor of 1 Kohm.
15.During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.
> 1024 Stable clock
Start Normal
Operation
DOFF
Stabl
e
(< +/- 0.1V DC per 50ns )
Fix High (or tied to VDDQ)
K
K
DDQ
V
DD
V
/
DDQ
DD
V
V
/
Clock Start
(
Clock Starts after DD
)
V
/
~
~
~
~
Unstable Clock
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1520V18-200BZXC 72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1520V18-200BZXI 72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1520V18-250BZC 72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1520V18-250BZI 72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1520V18-250BZXC 72-Mbit DDR-II SRAM 2-Word Burst Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1520V18-225BZC 制造商:Cypress Semiconductor 功能描述:2MX36 72M DDR-II BURST 2 SRAM - Bulk
CY7C1520V18-250BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2M x 36 1.8V DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1520V18-250BZCES 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 1.8V 72MBIT 2MX36 0.45NS 165FBGA - Bulk
CY7C1520V18-300BZC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 1.8V 72MBIT 2MX36 0.45NS 165FBGA - Bulk
CY7C1520XC 制造商:Cypress Semiconductor 功能描述:
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