參數(shù)資料
型號: CY7C1520V18-167BZXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 72-Mbit DDR-II SRAM 2-Word Burst Architecture
中文描述: 2M X 36 DDR SRAM, 0.5 ns, PBGA165
封裝: 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁數(shù): 11/28頁
文件大?。?/td> 457K
代理商: CY7C1520V18-167BZXC
CY7C1516V18
CY7C1527V18
CY7C1518V18
CY7C1520V18
Document #: 38-05563 Rev. *D
Page 11 of 28
Write Cycle Descriptions
[3, 9]
(CY7C1520V18)
BWS
0
L
BWS
1
L
BWS
2
L
BWS
3
L
K
K
Comments
L-H
During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are
written into the device.
During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are
written into the device.
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is
written into the device. D
[35:9]
will remain unaltered.
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is
written into the device. D
[35:9]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is
written into the device. D
[8:0]
and D
[35:18]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is
written into the device. D
[8:0]
and D
[35:18]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[26:18]
) is
written into the device. D
[17:0]
and D
[35:27]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[26:18]
) is
written into the device. D
[17:0]
and D
[35:27]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[35:27]
) is
written into the device. D
[26:0]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[35:27]
) is
written into the device. D
[26:0]
will remain unaltered.
No data is written into the device during this portion of a Write operation.
No data is written into the device during this portion of a Write operation.
L
L
L
L
L-H
L
H
H
H
L-H
L
H
H
H
L-H
H
L
H
H
L-H
H
L
H
H
L-H
H
H
L
H
L-H
H
H
L
H
L-H
H
H
H
L
L-H
H
H
H
L
L-H
H
H
H
H
H
H
H
H
L-H
L-H
Write Cycle Descriptions
[3, 9]
(CY7C1527V18)
BWS
0
L
K
K
Comments
L-H
During the Data portion of a Write sequence
,
the single byte (D
[8:0]
) is
written into the device.
During the Data portion of a Write sequence
,
the single byte (D
[8:0]
) is
written into the device.
No data is written into the device during this portion of a Write operation.
No data is written into the device during this portion of a Write operation.
L
L-H
H
H
L-H
L-H
Note:
9. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS
0
, NWS
1,
BWS
0
, BWS
1,
BWS
2
and BWS
3
can be altered on different
portions of a write cycle, as long as the set-up and hold requirements are achieved.
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CY7C1520V18-167BZXI 72-Mbit DDR-II SRAM 2-Word Burst Architecture
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