參數(shù)資料
型號： CY7C1486V33
廠商： Cypress Semiconductor Corp.
英文描述： 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM(72-Mb (2M x 36/4M x 18/1M x 72) 管道式同步SRAM)
中文描述： 72兆位（2米x 36/4M x 18/1M × 72）流水線同步靜態(tài)存儲器（72 - MB的（2米x 36/4M x 18/1M × 72）管道式同步靜態(tài)存儲器）
文件頁數(shù)： 1/32頁
文件大小： 1235K
代理商： CY7C1486V33
72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined Sync SRAM
CY7C1480V33
CY7C1482V33
CY7C1486V33
Cypress Semiconductor Corporation
Document #: 38-05283 Rev. *H
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised April 23, 2007
Features
Supports bus operation up to 250 MHz
Available speed grades are 250, 200, and 167 MHz
Registered inputs and outputs for pipelined operation
3.3V core power supply
2.5V/3.3V I/O operation
Fast clock-to-output times
— 3.0 ns (for 250 MHz device)
Provide high performance 3-1-1-1 access rate
User selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self timed writes
Asynchronous output enable
Single cycle chip deselect
CY7C1480V33, CY7C1482V33 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1486V33
available in Pb-free and non-Pb-free 209-ball FBGA
package
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM
integrates 2M x 36/4M x 18/1M × 72 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BW
X
,
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at the rising edge
of the clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see
“Pin Definitions” on page 7
and
“Truth Table”
on page 10
for further details). Write cycles can be one to two
or four bytes wide as controlled by the byte write control inputs.
GW when active LOW causes all bytes to be written.
The CY7C1480V33/CY7C1482V33/CY7C1486V33 operates
from a +3.3V core power supply while all outputs may operate
with either a +2.5 or +3.3V supply. All inputs and outputs are
JEDEC standard JESD8-5 compatible.
Selection Guide
250 MHz
3.0
500
120
200 MHz
3.0
500
120
167 MHz
3.4
450
120
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Note
AN1064, SRAM System Guidelines
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