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參數(shù)資料
| 型號： | CY7C1486V25-250BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| 中文描述： | 1M X 72 CACHE SRAM, 3 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1.76 MM HEIGHT, FBGA-209 |
| 文件頁數(shù)： | 9/31頁 |
| 文件大小： | 530K |
| 代理商： | CY7C1486V25-250BGI |
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CY7C1480V25
CY7C1482V25
CY7C1486V25
Document #: 38-05282 Rev. *G
Page 9 of 31
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQs is written into the
corresponding address location in the memory core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Because CY7C1480V25/CY7C1482V25/CY7C1486V25 is a
common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1480V25/CY7C1482V25/CY7C1486V25 provides
a two-bit wraparound counter, fed by A1: A0, that implements
either an interleaved or linear burst sequence. The interleaved
burst sequence is designed specifically to support Intel
Pentium applications. The linear burst sequence is designed
to support processors that follow a linear burst sequence. The
burst sequence is user selectable through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
ZZ Mode Electrical Characteristics
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
1
, CE
2
, CE
3
, ADSP, and ADSC must
remain inactive for the duration of t
ZZREC
after the ZZ input
returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A1: A0
A1: A0
00
01
01
00
10
11
11
10
Second
Address
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
10
11
00
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
00
01
10
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Truth Table
[2, 3, 4, 5, 6]
Description
Test Conditions
ZZ > V
DD
– 0.2V
ZZ > V
DD
– 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
120
2t
CYC
Unit
mA
ns
ns
ns
ns
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to sleep current
ZZ Inactive to exit sleep current
2t
CYC
2t
CYC
0
Operation
Add. Used
None
None
None
None
None
None
External
External
CE
1
H
L
L
L
L
X
L
L
CE
2
X
L
X
L
X
X
H
H
CE
3
X
X
H
X
H
X
L
L
ZZ
L
L
L
L
L
H
L
L
ADSP
X
L
L
H
H
X
L
L
ADSC
L
X
X
L
L
X
X
X
ADV
X
X
X
X
X
X
X
X
WRITE
X
X
X
X
X
X
X
X
OE CLK
X
X
X
X
X
X
L
H
DQ
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Sleep Mode, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Q
Tri-State
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
[+] Feedback
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