參數(shù)資料
型號: CY7C1482V25-250AXI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
中文描述: 4M X 18 CACHE SRAM, 3 ns, PQFP100
封裝: 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100
文件頁數(shù): 24/31頁
文件大?。?/td> 530K
代理商: CY7C1482V25-250AXI
CY7C1480V25
CY7C1482V25
CY7C1486V25
Document #: 38-05282 Rev. *G
Page 24 of 31
Read/Write Cycle Timing
[20, 22, 23]
Notes:
22.The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
23.GW is HIGH.
Switching Waveforms
(continued)
tCYC
tCL
CLK
ADSP
tADH
tADS
ADDRESS
tCH
OE
ADSC
CE
tAH
tAS
A2
tCEH
tCES
BWE,
BW
X
Data Out (Q)
High-Z
ADV
Single WRITE
D(A3)
A4
A5
A6
D(A5)
D(A6)
Data In (D)
BURST READ
Back-to-Back READs
High-Z
Q(A2)
Q(A1)
Q(A4)
Q(A4+1)
Q(A4+2)
tWEH
tWES
Q(A4+3)
tOEHZ
tDH
tDS
tOELZ
tCLZ
tCO
Back-to-Back
WRITEs
A1
DON’T CARE
UNDEFINED
A3
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CY7C1482V25-250BZC 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482V25-250BZI 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482V25-250BZXC 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482V25-250BZXI 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1486V25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
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