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參數(shù)資料
| 型號： | CY7C1481V25-133BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM |
| 中文描述： | 2M X 36 CACHE SRAM, 6.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165 |
| 文件頁數(shù)： | 1/30頁 |
| 文件大?。?/td> | 1028K |
| 代理商： | CY7C1481V25-133BZI |
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72-Mbit (2M x 36/4M x 18/1M x 72)
Flow-Through SRAM
CY7C1481V25
CY7C1483V25
CY7C1487V25
Cypress Semiconductor Corporation
Document #: 38-05281 Rev. *H
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised April 24, 2007
Features
Supports 133 MHz bus operations
2M x 36/4M x 18/1M x 72 common IO
2.5V core power supply (V
DD
)
2.5V or 1.8V IO supply (V
DDQ
)
Fast clock-to-output time
— 6.5 ns (133-MHz version)
Provide high-performance 2-1-1-1 access rate
User selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self timed write
Asynchronous output enable
CY7C1481V25, CY7C1483V25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1487V25
available in Pb-free and non-Pb-free 209-ball FBGA
package
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1481V25/CY7C1483V25/CY7C1487V25 is a 2.5V,
2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive edge triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address pipelining Chip Enable
(CE
1
), depth expansion Chip Enables (CE
2
and
CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BW
x
,
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.
The CY7C1481V25/CY7C1483V25/CY7C1487V25 enables
either interleaved or linear burst sequences, selected by the
MODE input pin. A HIGH selects an interleaved burst
sequence, while a LOW selects a linear burst sequence. Burst
accesses can be initiated with the Processor Address Strobe
(ADSP) or the cache Controller Address Strobe (ADSC)
inputs. Address advancement is controlled by the Address
Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1481V25/CY7C1483V25/CY7C1487V25 operates
from a +2.5V core power supply while all outputs may operate
with either a +2.5 or +1.8V supply. All inputs and outputs are
JEDEC-standard JESD8-5-compatible.
Note
1. For best practices recommendations, refer to the Cypress application note
System Design Guidelines
at
www.cypress.com
.
Selection Guide
133 MHz
100 MHz
Unit
Maximum Access Time
6.5
8.5
ns
Maximum Operating Current
305
275
mA
Maximum CMOS Standby Current
120
120
mA
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1481V25-133BZXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM |
| CY7C1481V25-133BZXI | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM |
| CY7C1483V25 | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM |
| CY7C1483V25-100AXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM |
| CY7C1483V25-100AXI | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM |
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