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參數(shù)資料
| 型號： | CY7C1480V33-250BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| 中文描述： | 2M X 36 CACHE SRAM, 3 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165 |
| 文件頁數(shù)： | 1/30頁 |
| 文件大?。?/td> | 398K |
| 代理商： | CY7C1480V33-250BZXC |
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72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined
Sync SRAM
CY7C1480V33
CY7C1482V33
CY7C1486V33
PRELIMINARY
Cypress Semiconductor Corporation
Document #: 38-05283 Rev. *C
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised December 3, 2004
Features
Supports bus operation up to 250 MHz
Available speed grades are 250, 200,167 MHz
Registered inputs and outputs for pipelined operation
3.3V core power supply
2.5V / 3.3V I/O operation
Fast clock-to-output times
— 3.0 ns (for 250-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 167-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Single Cycle Chip Deselect
CY7C1480V33 and CY7C1482V33 offered in
JEDEC-standard lead-free 100-pin TQFP, 165-Ball fBGA
packages. CY7C1486V33 available in 209-Ball BGA
packages
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” Sleep Mode Option
Functional Description
[1]
The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM
integrates 2,097,152 x 36/4,194,304 x 18,1,048,576 × 72
SRAM cells with advanced synchronous peripheral circuitry
and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE
1
), depth-expansion Chip Enables (CE
2
and
CE
3
), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (BW
X
, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the
ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1480V33/CY7C1482V33/CY7C1486V33 operates
from a +3.3V core power supply while all outputs may operate
with either a +2.5 or +3.3V supply. All inputs and outputs are
JEDEC-standard JESD8-5-compatible.
Selection Guide
250 MHz
3.0
500
120
200 MHz
3.0
500
120
167 MHz
3.4
450
120
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Shaded areas contain advance information.
Please contact your local Cypress sales representative for availability of these parts.
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1480V33 | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| CY7C1480V33-167AXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| CY7C1480V33-167BZC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| CY7C1480V33-167BZXC | JUMPER WIRE 0.2 LONG PKG OF 200 |
| CY7C1482V33-167AXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1480V33-250BZXI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1480XC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1481BV25-133AXI | 功能描述:靜態(tài)隨機(jī)存取存儲器 72MB (2Mx36) 2.5v 133MHz 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1481BV33-133AXI | 功能描述:靜態(tài)隨機(jī)存取存儲器 72MB (2Mx36) 3.3v 133MHz 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1481BV33-133BZI | 功能描述:靜態(tài)隨機(jī)存取存儲器 72MB (2Mx36) 3.3v 133MHz 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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