參數(shù)資料
型號： CY7C1473V33-133AXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
中文描述： 4M X 18 ZBT SRAM, 6.5 ns, PQFP100
封裝： 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100
文件頁數(shù)： 22/29頁
文件大小： 375K
代理商： CY7C1473V33-133AXC
PRELIMINARY
CY7C1471V33
CY7C1473V33
CY7C1475V33
Document #: 38-05288 Rev. *E
Page 22 of 29
Switching Characteristics
Over the Operating Range
[21, 22]
Parameter
t
POWER‘
Clock
t
CYC
t
CH
t
CL
Output Times
t
CDV
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Set-up Times
t
AS
t
ALS
t
WES
t
CENS
t
DS
t
CES
Hold Times
t
AH
t
ALH
t
WEH
t
CENH
t
DH
t
CEH
Notes:
17.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially, before a Read or Write operation
can be initiated.
18.t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
19.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
20.This parameter is sampled and not 100% tested.
21.Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
DDQ
= 2.5V.
22.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Description
133 MHz
Min.
1
100 MHz
Min.
1
Unit
ms
Max.
Max.
Clock Cycle Time
Clock HIGH
Clock LOW
7.5
2.5
2.5
10
3.0
3.0
ns
ns
ns
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z
[18, 19, 20]
Clock to High-Z
[18, 19, 20]
OE LOW to Output Valid
OE LOW to Output Low-Z
[18, 19, 20]
OE HIGH to Output High-Z
[18, 19, 20]
6.5
8.5
ns
ns
ns
ns
ns
ns
ns
2.5
3.0
2.5
3.0
3.8
3.0
4.5
3.8
0
0
3.0
4.0
Address Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
WE, BW
X
Set-up Before CLK Rise
CEN Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
Address Hold After CLK Rise
ADV/LD Hold After CLK Rise
WE, BW
X
Hold After CLK Rise
CEN Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
相關(guān)PDF資料
PDF描述
CY7C1473V33-133BZC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V33-100BZC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V33-100BZXC LME Series; Mounting Style: Direct mount; Functions: Continuous light; Light Type: LED; Rated Voltage: 24V AC/DC; Style: 2 - light; Color: Red, Green (other color combo avail); Diameter: 60; Applicable Model: LME
CY7C1471V33-133BZXC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V33-100AXC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
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