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參數(shù)資料
| 型號： | CY7C1473V33-100BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
| 中文描述： | 4M X 18 ZBT SRAM, 8.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165 |
| 文件頁數(shù)： | 1/29頁 |
| 文件大小： | 375K |
| 代理商： | CY7C1473V33-100BZC |
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PRELIMINARY
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through
SRAM with NoBL Architecture
CY7C1471V33
CY7C1473V33
CY7C1475V33
Cypress Semiconductor Corporation
Document #: 38-05288 Rev. *E
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised December 5, 2004
Features
No Bus Latency (NoBL) architecture eliminates
dead cycles between write and read cycles.
Can support up to 133-MHz bus operations with zero
wait states
Data is transferred on every clock
Pin compatible and functionally equivalent to ZBT
devices
Internally self-timed output buffer control to eliminate
the need to use OE
Registered inputs for flow-through operation
Byte Write capability
3.3V/2.5V I/O power supply
Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 8.5 ns (for 100-MHz device)
Clock Enable (CEN) pin to enable clock and suspend
operation
Synchronous self-timed writes
Asynchronous Output Enable
Offered in JEDEC-standard lead-free 100 TQFP, and
165-ball fBGA packages for CY7C1471V33 and
CY7C1473V33. 209-ball fBGA package for
CY7C1475V33.
Three chip enables for simple depth expansion.
Automatic Power-down feature available using ZZ
mode or CE deselect.
JTAG boundary scan for BGA and fBGA packages
Burst Capability—linear or interleaved burst order
Low standby power
Functional Description
[1]
The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are
3.3V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through
Burst SRAMs designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1471V33, CY7C1473V33 and
CY7C1475V33 are equipped with the advanced No Bus
Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BW
X
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Selection Guide
133 MHz
6.5
335
150
100 MHz
8.5
305
150
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1473V33-100BZXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
| CY7C1473V33-133AXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
| CY7C1473V33-133BZC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
| CY7C1471V33-100BZC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
| CY7C1471V33-100BZXC | LME Series; Mounting Style: Direct mount; Functions: Continuous light; Light Type: LED; Rated Voltage: 24V AC/DC; Style: 2 - light; Color: Red, Green (other color combo avail); Diameter: 60; Applicable Model: LME |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1474BV25-167BGC | 功能描述:靜態(tài)隨機存取存儲器 1Mx72, 2.5V NoBL PL RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1474BV25-167BGCT | 功能描述:靜態(tài)隨機存取存儲器 1Mx72, 2.5V NoBL PL RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1474BV25-167BGI | 功能描述:靜態(tài)隨機存取存儲器 1Mx72, 2.5V NoBL PL RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1474BV25-167BGIT | 功能描述:靜態(tài)隨機存取存儲器 1Mx72 2.5V NoBL PL 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1474BV25-200BGC | 功能描述:靜態(tài)隨機存取存儲器 1Mx72, 2.5V NoBL PL RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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