參數(shù)資料
型號(hào)： CY7C145AV-25JC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM
中文描述： 8K X 9 DUAL-PORT SRAM, 25 ns, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 10/20頁(yè)
文件大?。?/td> 301K
代理商： CY7C145AV-25JC
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document #: 38-06051 Rev. *A
Page 10 of 20
Notes:
29. R/W must be HIGH during all address transitions.
30. A write occurs during the overlap (t
or t
) of a LOW CE or SEM.
31. t
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
32. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or (t
+ t
) to allow the I/O drivers to turn off and
data to be placed on the bus for the required t
SD
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse
can be as short as the specified t
.
33. Transition is measured
±
500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
34. To access RAM, CE = V
, SEM = V
.
35. During this period, the I/O pins are in the output state, and input signals must not be applied.
36. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Switching Waveforms
(continued)
t
AW
t
WC
t
PWE
t
HD
t
SD
t
HA
CE
R/W
OE
DATAOUT
DATA IN
ADDRESS
t
HZOE
t
SA
t
HZWE
t
LZWE
Write Cycle No. 1: R/W Controlled Timing
[29, 30, 31, 32]
[33]
[33]
[32]
[34]
[35]
[35]
t
AW
t
WC
t
SCE
t
HD
t
SD
t
HA
CE
R/W
DATA IN
ADDRESS
t
SA
Write Cycle No. 2: CE Controlled Timing
[29, 30, 31, 36]
[34]
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