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參數(shù)資料
| 型號： | CY7C144AV |
| 英文描述： | Memory |
| 中文描述： | 內(nèi)存 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 301K |
| 代理商： | CY7C144AV |
3.3V 4K/8K/16K/32K x 8/9
Dual-Port Static RAM
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-06051 Rev. *A
Revised December 27, 2002
25/0251
Features
True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
4K/8K/16K/32K x 8 organizations
(CY7C0138AV/144AV/006AV/007AV)
4K/8K/16K/32K x 9 organizations
(CY7C0139AV/145AV/016AV/017AV)
0.35-micron CMOS for optimum speed/power
High-speed access: 20/25 ns
Low operating power
— Active: ICC = 115 mA (typical)
— Standby: ISB3 = 10 A (typical)
Fully asynchronous operation
Automatic power-down
Expandable data bus to 16/18 bits or more using Master/
Slave chip select when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Pin select for Master or Slave
Commercial and Industrial Temperature Ranges
Available in 68-pin PLCC (all) and 64-pin TQFP
(7C006AV & 7C144AV)
Pin-compatible and functionally equivalent to
IDT70V05, 70V06, and 70V07.
Notes:
1.
I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices.
2.
A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices; A0–A14 for 32K devices;
3.
BUSY is an output in master mode and an input in slave mode.
I/O
Control
Address
Decode
A0L–A11–14L
CEL
OEL
R/WL
BUSYL
I/O
Control
Interrupt
Semaphore
Arbitration
SEML
INTL
M/S
A0L–A11–14L
True Dual-Ported
RAM Array
A0R–A11–14R
CER
OER
R/WR
BUSYR
SEMR
INTR
Address
Decode
A0R–A11–14R
[1]
[3]
R/WL
OEL
I/O0L–I/O7/8L
CEL
R/WR
OER
I/O0R–I/O7/8R
CER
12–15
8/9
12–15
8/9
12–15
[2]
Logic Block Diagram
For the most recent information, visit the Cypress web site at www.cypress.com
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C144AV-20AC | x8 Dual-Port SRAM |
| CY7C144AV-20JC | x8 Dual-Port SRAM |
| CY7C144AV-25AC | x8 Dual-Port SRAM |
| CY7C144AV-25JC | x8 Dual-Port SRAM |
| CY7C146-35JCT | x8 Dual-Port SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C144AV-20AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Dual 3.3V 64K-Bit 8K x 8 20ns 64-Pin TQFP |
| CY7C144AV-25AC | 功能描述:IC SRAM 64KB DUAL 64-TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
| CY7C144AV-25ACKJ | 制造商:Cypress Semiconductor 功能描述: |
| CY7C144AV25AI | 制造商:CYPRESS 功能描述:* |
| CY7C144AV-25AI | 制造商:Rochester Electronics LLC 功能描述:3.3V 8K X 8 ASYNC DUAL PORT SRAM - Bulk |
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