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參數(shù)資料
| 型號： | CY7C144 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8K x 9 Dual-Port Static RAM(8K x 9 雙端口靜態(tài) RAM) |
| 中文描述： | 8K的× 9雙端口靜態(tài)存儲器（8K的× 9雙端口靜態(tài)RAM）的 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 612K |
| 代理商： | CY7C144 |
8K x 8/9 Dual-Port Static RAM
with SEM, INT, BUSY
CY7C144
CY7C145
Cypress Semiconductor Corporation
Document #: 38-06034 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised September 6, 2005
Features
True Dual-Ported memory cells that allow simultaneous
reads of the same memory location
8K x 8 organization (CY7C144)
8K x 9 organization (CY7C145)
0.65-micron CMOS for optimum speed/power
High-speed access: 15ns
Low operating power: I
CC
= 160 mA (max.)
Fully asynchronous operation
Automatic power-down
TTL compatible
Master/Slave select pin allows bus width expansion to
16/18 bits or more
Busy arbitration scheme provided
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Available in 68-pin PLCC, 64-pin and 80-pin TQFP
Pb-Free packages available
Functional Description
The CY7C144 and CY7C145 are high-speed CMOS 8K x 8
and 8K x 9 dual-port static RAMs. Various arbitration schemes
are included on the CY7C144/5 to handle situations when
multiple processors access the same piece of data. Two ports
are provided permitting independent, asynchronous access
for reads and writes to any location in memory. The
CY7C144/5 can be utilized as a standalone 64/72-Kbit
dual-port static RAM or multiple devices can be combined in
order to function as a 16/18-bit or wider master/slave dual-port
static RAM. An M/S pin is provided for implementing 16/18-bit
or wider memory applications without the need for separate
master and slave devices or additional discrete logic. Appli-
cation areas include interprocessor/multiprocessor designs,
communications
status
video/graphics memory.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags,
BUSY and INT, are provided on each port. BUSY signals that
the port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from
one port to the other to indicate that a shared resource is in
use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared
resource is in use. An automatic power-down feature is
controlled independently on each port by a chip enable (CE)
pin or SEM pin.
buffering,
and
dual-port
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
R/W
L
CE
L
OE
L
A
12L
A
0L
A
0R
A
12R
R/W
R
CE
R
OE
R
CE
R
OE
R
CE
L
OE
L
R/W
L
R/W
R
7L
I/O
0L
I/O
7R
I/O
0R
INTERRUPT
SEMAPHORE
ARBITRATION
CONTROL
I/O
COI/O
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
SEM
L
INT
L
INT
R
R
BUSY
L
BUSY
R
M/S
(7C145) I/O
8L
I/O
8R
(7C145)
Logic Block Diagram
[1, 2]
[2]
[1, 2]
[2]
CY7C1458K x 8/9 Dual-Port Static RAM
CY7C144
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C146-25JC | 2Kx8 Dual-Port Static RAM |
| CY7C146-30JC | 2Kx8 Dual-Port Static RAM |
| CY7C146-30JI | 2Kx8 Dual-Port Static RAM |
| CY7C146-30NC | 2Kx8 Dual-Port Static RAM |
| CY7C146-35JC | 2Kx8 Dual-Port Static RAM |
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