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參數(shù)資料
| 型號： | CY7C1426AV18 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 36-Mbit QDR-II SRAM 4-Word Burst Architecture(4字Burst結(jié)構(gòu),36-Mbit QDR-II SRAM) |
| 中文描述： | 的36 - Mbit QDR - II型SRAM的4字突發(fā)架構(gòu)（4字突發(fā)結(jié)構(gòu),36 - Mbit的QDR - II型的SRAM） |
| 文件頁數(shù)： | 1/28頁 |
| 文件大?。?/td> | 1130K |
| 代理商： | CY7C1426AV18 |
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36-Mbit QDR-II SRAM 4-Word Burst
Architecture
CY7C1411AV18
CY7C1426AV18
CY7C1413AV18
CY7C1415AV18
Cypress Semiconductor Corporation
Document Number: 38-05614 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised June 26, 2006
Features
Separate Independent Read and Write data ports
— Supports concurrent transactions
300-MHz clock for high bandwidth
4-Word Burst for reducing address bus frequency
Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 600 MHz) at 300 MHz
Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches
Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
Single multiplexed address input bus latches address
inputs for both Read and Write ports
Separate Port Selects for depth expansion
Synchronous internally self-timed writes
Available in x8, x9, x18, and x36 configurations
Full data coherency providing most current data
Core V
DD
= 1.8 (±0.1V); I/O V
DDQ
= 1.4V to V
DD
Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
Offered in both lead-free and non lead-free packages
Variable drive HSTL output buffers
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1411AV18 – 4M x 8
CY7C1426AV18 – 4M x 9
CY7C1413AV18 – 2M x 18
CY7C1415AV18 – 1M x 36
Functional Description
The CY7C1411AV18, CY7C1426AV18, CY7C1413AV18, and
CY7C1415AV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II architecture. QDR-II architecture
consists of two separate ports to access the memory array.
The Read port has dedicated Data Outputs to support Read
operations and the Write port has dedicated Data Inputs to
support Write operations. QDR-II architecture has separate
data inputs and data outputs to completely eliminate the need
to “turn-around” the data bus required with common I/O
devices. Access to each port is accomplished through a
common address bus. Addresses for Read and Write
addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the QDR-II Read and Write ports are
completely independent of one another. In order to maximize
data throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with four 8-bit words (CY7C1411AV18) or 9-bit
words (CY7C1426AV18) or 18-bit words (CY7C1413AV18) or
36-bit words (CY7C1415AV18) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K and
K and C and C), memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
300 MHz
300
925
278 MHz
278
875
250 MHz
250
800
200 MHz
200
700
167 MHz
167
600
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
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| CY7C1427AV18 | 36-Mbit DDR-II SRAM 2-Word Burst Architecture(2字Burst結(jié)構(gòu)，36-Mbit DDR-II SRAM) |
| CY7C1441AV33 | 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM(36-Mb (1M x 36/2M x 18/512K x 72)流通式SRAM) |
| CY7C1443AV33 | 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM(36-Mb (1M x 36/2M x 18/512K x 72)流通式SRAM) |
| CY7C1447AV33 | 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM(36-Mb (1M x 36/2M x 18/512K x 72)流通式SRAM) |
| CY7C1444AV33 | 36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM(36-Mb (1M x 36/2M x 18)管道式DCD同步SRAM) |
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| CY7C1426AV18-167BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 4Mx9 QDR II Burst 4 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1426AV18-200BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 4Mx9 QDR II Burst 4 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1426AV18-250BZC | 功能描述:靜態(tài)隨機(jī)存取存儲器 4Mx9 QDR II Burst 4 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1426AV18-250BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 4Mx9 QDR II Burst 4 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1426AV18-300BZC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 1.8V 36MBIT 4M X 9 0.45NS 165FBGA - Bulk |
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