參數(shù)資料
型號: CY7C1418BV18-200BZXI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 36-Mbit DDR-II SRAM 2-Word Burst Architecture
中文描述: 2M X 18 DDR SRAM, 0.45 ns, PBGA165
封裝: 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁數(shù): 9/28頁
文件大?。?/td> 1132K
代理商: CY7C1418BV18-200BZXI
PRELIMINARY
CY7C1416BV18
CY7C1427BV18
CY7C1418BV18
CY7C1420BV18
Document Number: 001-07033 Rev. *B
Page 9 of 28
Application Example
[1]
Truth Table for DDR-II
[2, 3, 4, 5, 6, 7]
Operation
K
LD
L
R/W
L
DQ
DQ
Write Cycle:
Load address; wait one cycle; input write data on
consecutive K and K rising edges.
Read Cycle:
Load address; wait one and a half cycle; read data on
consecutive C and C rising edges.
NOP: No Operation
Standby: Clock Stopped
L-H
D(A) at K(t + 1)
D(A + 1) at K(t + 1)
L-H
L
H
Q(A) at C(t + 1)
Q(A + 1) at C(t + 2)
L-H
H
X
X
X
High-Z
Previous State
High-Z
Previous State
Stopped
Burst Address Table
(CY7C1427BV18, CY7C1418BV18)
First Address (External)
X..X0
X..X1
Second Address (Internal)
X..X1
X..X0
Notes:
1. The above application shows two DDR-II used.
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW,
represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. On CY7C1418BV18 and CY7C1420BV18, “A” represents address location latched by the devices when transaction was initiated and A + 1 represents the
addresses sequence in the burst. On CY7C1416BV18 and CY7C1427BV18 “A” represents A + ‘0’ and A2 represents A + ‘1’.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
LD#
Vterm = 0.75V
Vterm = 0.75V
C C#
R/W#
ZQ
CQ/CQ#
K#
DQ
A
LD#
C C#
R/W#
ZQ
CQ/CQ#
K#
DQ
A
BUS
MASTER
(CPU
or
ASIC)
SRAM#1
SRAM#2
DQ
Addresses
Cycle Start#
R/W#
Return CLK
Source CLK
Return CLK#
Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
R = 50
ohms
R = 250
ohms
R
= 250ohms
[+] Feedback
相關PDF資料
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CY7C1418BV18-250BZC 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1418BV18-250BZI 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1418BV18-250BZXC 36-Mbit DDR-II SRAM 2-Word Burst Architecture
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