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    參數(shù)資料
    型號(hào): CY7C1418BV18-200BZC
    廠商: CYPRESS SEMICONDUCTOR CORP
    元件分類: DRAM
    英文描述: 36-Mbit DDR-II SRAM 2-Word Burst Architecture
    中文描述: 2M X 18 DDR SRAM, 0.45 ns, PBGA165
    封裝: 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
    文件頁數(shù): 17/28頁
    文件大?。?/td> 1132K
    代理商: CY7C1418BV18-200BZC
    PRELIMINARY
    CY7C1416BV18
    CY7C1427BV18
    CY7C1418BV18
    CY7C1420BV18
    Document Number: 001-07033 Rev. *B
    Page 17 of 28
    Identification Register Definitions
    Instruction
    Field
    Revision
    Number (31:29)
    Cypress Device
    ID (28:12)
    Cypress JEDEC
    ID (11:1)
    Value
    Description
    Version number.
    CY7C1416BV18
    001
    CY7C1420BV18
    001
    CY7C1427BV18
    001
    CY7C1418BV18
    001
    11010100010000111
    11010100010001111
    11010100010010111 11010100010100111 Defines the type
    of SRAM.
    Allows unique
    identification of
    SRAM vendor.
    Indicate the
    presence of an
    ID register.
    00000110100
    00000110100
    00000110100
    00000110100
    ID Register
    Presence (0)
    1
    1
    1
    1
    Scan Register Sizes
    Register Name
    Instruction
    Bypass
    ID
    Boundary Scan
    Bit Size
    3
    1
    32
    109
    Instruction Codes
    Instruction
    EXTEST
    IDCODE
    Code
    000
    001
    Description
    Captures the Input/Output ring contents.
    Loads the ID register with the vendor ID code and places the register between TDI and TDO.
    This operation does not affect SRAM operation.
    Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
    Forces all SRAM output drivers to a High-Z state.
    Do Not Use: This instruction is reserved for future use.
    Captures the Input/Output ring contents. Places the boundary scan register between TDI and
    TDO. Does not affect the SRAM operation.
    Do Not Use: This instruction is reserved for future use.
    Do Not Use: This instruction is reserved for future use.
    Places the bypass register between TDI and TDO. This operation does not affect SRAM
    operation.
    SAMPLE Z
    010
    RESERVED
    SAMPLE/PRELOAD
    011
    100
    RESERVED
    RESERVED
    BYPASS
    101
    110
    111
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