- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379075 > CY7C1418BV18-167BZXI (CYPRESS SEMICONDUCTOR CORP) 36-Mbit DDR-II SRAM 2-Word Burst Architecture PDF資料下載
參數(shù)資料
| 型號： | CY7C1418BV18-167BZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| 中文描述： | 2M X 18 DDR SRAM, 0.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 1132K |
| 代理商： | CY7C1418BV18-167BZXI |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
PRELIMINARY
CY7C1416BV18
CY7C1427BV18
CY7C1418BV18
CY7C1420BV18
Document Number: 001-07033 Rev. *B
Page 7 of 28
Functional Overview
The CY7C1416BV18, CY7C1420BV18, CY7C1427BV18, and
CY7C1418BV18 are synchronous pipelined Burst SRAMs
equipped with a DDR interface which operates with a read
latency of one and half cycles when DOFF pin is tied HIGH.
When DOFF pin is set LOW or connected to V
SS
the device
behave in DDR-I mode with a read latency of one clock cycle.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing
is referenced to the rising edge of the output clocks (C/C or
K/K when in single clock mode).
All synchronous data inputs (D
[x:0]
) pass through input
registers controlled by the rising edge of the input clocks (K
and K). All synchronous data outputs (Q
[x:0]
) pass through
output registers controlled by the rising edge of the output
clocks (C/C or K/K when in single-clock mode).
All synchronous control (R/W, LD, BWS
[0:X]
) inputs pass
through input registers controlled by the rising edge of the
input clock (K).
CY7C1427BV18 is described in the following sections. The
same
basic
descriptions
CY7C1420BV18, and CY7C1418BV18.
apply
to
CY7C1416BV18,
Read Operations for DDR-II
The CY7C1427BV18 is organized internally as a single array
of 2M x 18. Accesses are completed in a burst of two
sequential 18-bit data words. Read operations are initiated by
asserting R/W
HIGH and LD LOW at the rising edge of the
positive input clock (K). The address presented to Address
inputs is stored in the Read address register and the least
significant bit of the address is presented to the burst counter.
The burst counter increments the address in a linear fashion.
Following the next K clock rise the corresponding 18-bit word
of data from this address location is driven onto the Q
[17:0]
using C as the output timing reference. On the subsequent
rising edge of C the next 18-bit data word from the address
location generated by the burst counter is driven onto the
Q
[17:0]
. The requested data will be valid 0.45 ns from the rising
edge of the output clock (C or C, or K and K when in single
clock mode, 200-MHz and 250-MHz device). In order to
maintain the internal logic, each read access must be allowed
CQ
Output-
Clock
CQ is referenced with respect to C
. This is a free running clock and is synchronized to the Input
clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to
K. The timings for the echo clocks are shown in the AC Timing table.
CQ is referenced with respect to C
. This is a free running clock and is synchronized to the Input
clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to
K. The timings for the echo clocks are shown in the AC Timing table.
Output Impedance Matching Input
. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to
V
DDQ
, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
DLL Turn Off, active LOW
. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
For normal operation, this pin should be pulled HIGH through 10-Kohm or less pull-up resistor.
More details on this operation can be found in the application note, “DLL Considerations in
QDRII/DDRII”. The device will behave in DDR-I mode when the DLL is turned off. In this mode,
the device can be operated at a frequency of up to 167MHz with DDR-I timing.
TDO for JTAG
.
TCK pin for JTAG
.
TDI pin for JTAG
.
TMS pin for JTAG
.
Not connected to the die
. Can be tied to any voltage level.
Not connected to the die
. Can be tied to any voltage level.
Not connected to the die
. Can be tied to any voltage level.
Not connected to the die
. Can be tied to any voltage level.
Reference Voltage Input
. Static input used to set the reference level for HSTL inputs and Outputs
as well as AC measurement points.
Power Supply
Power supply inputs to the core of the device
.
Ground
Ground for the device
.
Power Supply
Power supply inputs for the outputs of the device
.
CQ
Output-
Clock
ZQ
Input
DOFF
Input
TDO
TCK
TDI
TMS
NC
NC/72M
NC/144M
NC/288M
V
REF
Output
Input
Input
Input
N/A
N/A
N/A
N/A
Input-
Reference
V
DD
V
SS
V
DDQ
Pin Definitions
(continued)
Pin Name
I/O
Pin Description
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1418BV18-200BZC | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1418BV18-200BZI | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1418BV18-200BZXC | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1418BV18-200BZXI | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1418BV18-250BZC | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1418BV18-250BZC | 功能描述:靜態(tài)隨機存取存儲器 2Mx18 DDR II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1418BV18-250BZI | 功能描述:靜態(tài)隨機存取存儲器 2Mx18 DDR-II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1418BV18-250BZXC | 功能描述:靜態(tài)隨機存取存儲器 2Mx18 DDR II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1418BV18-267BZXC | 功能描述:靜態(tài)隨機存取存儲器 2Mx18 DDR-II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1418JV18-300BZC | 功能描述:靜態(tài)隨機存取存儲器 2Mx18 DDR II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。