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參數(shù)資料
| 型號： | CY7C1394BV18-167BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| 中文描述： | 512K X 36 DDR SRAM, 0.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 27/27頁 |
| 文件大?。?/td> | 446K |
| 代理商： | CY7C1394BV18-167BZXC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁
CY7C1392BV18
CY7C1992BV18
CY7C1393BV18
CY7C1394BV18
Document Number: 38-05623 Rev. *C
Page 27 of 27
Document History Page
Document Title: CY7C1392BV18/CY7C1992BV18/CY7C1393BV18/CY7C1394BV18 18-Mbit DDR-II SIO SRAM 2-Word
Burst Architecture
Document Number: 38-05623
Orig. of
Change
**
252474
See ECN
SYT
New data sheet
*A
325581
See ECN
SYT
Removed CY7C1992BV18 from the title
Included 300-MHz Speed Bin
Added Industrial Temperature Grade
Replaced TBDs for I
DD
and I
SB1
specs
Replaced the TBDs on the Thermal Characteristics Table to
Θ
JA
= 28.51
°
C/W
and
Θ
JC
= 5.91
°
C/W
Replaced TBDs in the Capacitance Table for the 165 FBGA Package
Changed the package diagram from BB165E (15 x 17 x 1.4 mm) to BB165D
(13 x 15 x 1.4 mm)
Added Lead-Free Product Information
Updated the Ordering Information by Shading and Unshading MPNs as per
availability
*B
413997
See ECN
NXR
Converted from Preliminary to Final
Added CY7C1992BV18 part number to the title
Added 278-MHz speed Bin
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed C/C Pin Description in the features section and Pin Description
Added power-up sequence details and waveforms
Added foot notes #15, 16, 17 on page# 18
Replaced Three-state with Tri-state
Changed the description of I
X
from Input Load Current to Input Leakage
Current on page# 19
Modified the I
DD
and I
SB
values
Modified test condition in Footnote #18 on page# 19 from V
DDQ
< V
DD
to
V
DDQ
< V
DD
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated the Ordering Information
*C
472384
See ECN
NXR
Modified the ZQ Definition from Alternately, this pin can be connected directly
to V
DD
to Alternately, this pin can be connected directly to V
DDQ
Included Maximum Ratings for Supply Voltage on V
DDQ
Relative to GND
Changed the Maximum Ratings for DC Input Voltage from V
DDQ
to V
DD
Changed t
TH
and t
TL
from 40 ns to 20 ns, changed t
TMSS
, t
TDIS
, t
CS
, t
TMSH
,
t
TDIH
, t
CH
from
10 ns to 5 ns and changed t
TDOV
from 20 ns to 10 ns in TAP AC
Switching Characteristics table
Modified Power-Up waveform
Changed the Maximum rating of Ambient Temperature with Power Applied
from –10°C to +85°C to –55°C to +125°C
Added additional notes in the AC parameter section
Modified AC Switching Waveform
Corrected the typo In the AC Switching Characteristics Table
Updated the Ordering Information Table
REV.
ECN No.
Issue Date
Description of Change
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1394BV18-167BZXI | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1394BV18-200BZC | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1394BV18-200BZI | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1394BV18-200BZXC | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1394BV18-200BZXI | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1399-12VC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 256K-Bit 32K x 8 12ns 28-Pin SOJ 制造商:Rochester Electronics LLC 功能描述:R ASSET CODE/B REV - Bulk |
| CY7C139912ZC | 制造商:CYP 功能描述:* |
| CY7C1399-12ZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1399-15VC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 256K-Bit 32K x 8 15ns 28-Pin SOJ 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C139915VI | 制造商:CYPRESS 功能描述:* |
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